SL74HC112
Dual J-K Flip-Flop with Set and Reset
High-Performance Silicon-Gate CMOS
The SL74HC112 is identical in pinout to the LS/ALS112. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
Each flip-flop is negative-edge clocked and has active-low
asynchronous Set and Reset inputs.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0
µA
•
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC112N Plastic
SL74HC112D SOIC
T
A
= -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Set
L
H
L
H
H
H
H
H
PIN 16=V
CC
PIN 8 = GND
H
H
Reset
H
L
L
H
H
H
H
H
H
H
L
H
Clock
X
X
X
J
X
X
X
L
L
H
H
X
X
X
K
X
X
X
L
H
L
H
X
X
X
Outputs
Q
H
L
L
*
Q
L
H
L
*
No Change
L
H
Toggle
No Change
No Change
No Change
H
L
* Both output will remain low as long as Set and Reset are
low, but the output states are unpredictable if Set and Reset
go high simultaneously
X = Don’t Care
SLS
System Logic
Semiconductor