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SL74HC138D 参数 Datasheet PDF下载

SL74HC138D图片预览
型号: SL74HC138D
PDF下载: 下载PDF文件 查看货源
内容描述: 1 - 8解码器/多路解复用器 [1-of-8 Decoder/Demultiplexer]
分类和应用: 解码器解复用器
文件页数/大小: 5 页 / 54 K
品牌: SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
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SL74HC138
1-of-8 Decoder/Demultiplexer
High-Performance Silicon-Gate CMOS
The SL74HC138 is identical in pinout to the LS/ALS138. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
The SL74HC138 decodes a three-bit Address to one-of-eight active-
low outputs. This device features three Chip Select inputs, two active-
low and one active-high to facilitate the demultiplexing, cascading, and
chip-selecting functions. The demultiplexing function is accomplished
by using the Address inputs to select the desired device output; one
of the Chip Selects is used as a data input while the other Chip Selects
are held in their active states.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
µA
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC138N Plastic
SL74HC138D SOIC
T
A
= -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
CS1 CS2 CS3
X X H
X H X
L X X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
A2 A1 A0
X X X
X X X
X X X
LL L
L L H
L H L
L H H
H L L
H L H
H H L
H H H
Outputs
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
H H H H H H H H
H H H H H H H H
H H H H H H H H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
PIN 16 =V
CC
PIN 8 = GND
L H H H
H L H H
H H L H
H H H L
H = high level (steady state)
L = low level (steady state)
X = don’t care
SLS
System Logic
Semiconductor