SL74HC193
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
f
max
Parameter
Minimum Clock Frequency (50% Duty Cycle)
(Figures 1 and 6)
Maximum Propagation Delay, Clock to Q (Figures
1 and 6)
Maximum Propagation Delay, PL to Q
(Figures 3 and 6)
Maximum Propagation Delay, Clock to Terminal
Count (Figures 2 and 6)
Maximum Output Transition Time,Any Output
(Figures 1 and 6)
Maximum Input Capacitance
Power Dissipation Capacitance (Per Package)
C
PD
Used to determine the no-load dynamic power
consumption: P
D
=C
PD
V
CC2
f+I
CC
V
CC
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
-
Guaranteed Limit
25
°C
to
-55°C
12
36
43
215
43
37
215
43
37
125
25
21
75
15
13
10
≤85°C
3.2
16
19
270
54
46
270
54
46
155
31
26
95
20
18
10
≤125°C
2.6
13
15
325
65
55
325
65
55
190
38
32
110
23
20
10
Unit
MHz
t
PLH
, t
PHL
ns
t
PLH
, t
PHL
ns
t
PLH
, t
PHL
ns
t
TLH
, t
THL
ns
C
IN
pF
Typical @25°C,V
CC
=5.0 V
60
pF
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
t
su
Parameter
Minimum Setup Time, Pn to PL
(Figure 4)
Minimum Hold Time, Pn to PL (Figure
4)
Minimum Pulse Width, Clock (Figure
1)
Minimum Pulse Width, PL
(Figure 3)
Minimum Pulse Width, MR
(Figure 5)
Minimum Input Rise and Fall Times
(Figure 1)
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Guaranteed Limit
25
°C
to -55°C
100
20
18
0
0
0
150
30
26
100
20
17
100
20
17
100
500
400
≤85°C
125
35
22
0
0
0
190
38
33
125
25
26
125
25
26
100
500
400
≤125°C
150
30
26
0
0
0
225
45
38
150
30
26
150
30
26
100
500
400
Unit
ns
t
h
ns
t
w
ns
t
w
ns
t
w
ns
t
r
, t
f
ns
SLS
System Logic
Semiconductor
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
