SL74HC323
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
f
max
Parameter
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 5)
Maximum Propagation Delay, Clock to Q
A
’ or Q
H
’
(Figures 1 and 5)
Maximum Propagation Delay, Clock to Q
A
or Q
H
(Figures 1 and 5)
Maximum Propagation Delay , OE1, OE2, S1, or S2
to Q
A
thru Q
H
(Figures 3 and 6)
Maximum Propagation Delay , OE1, OE2, S1, or S2
to Q
A
thru Q
H
(Figures 3 and 6)
Maximum Output Transition Time, Q
A
thru Q
H
(Figures 1 and 5)
Maximum Output Transition Time, Q
A
’ or Q
H
’
(Figures 1 and 5)
Maximum Input Capacitance
Maximum Three-State Output Capacitance
(Output in High-Impedance State), Q
A
thru Q
H
Power Dissipation Capacitance (Per Package),
Outputs Enable
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC2
f+I
CC
V
CC
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
-
-
Guaranteed Limit
25
°C
to
-55°C
5.0
25
29
170
34
29
160
32
27
150
30
26
150
30
26
60
12
10
75
15
13
10
15
≤85
°C
4.0
20
24
215
43
37
200
40
34
190
38
33
190
38
33
75
15
13
95
19
16
10
15
≤125
°C
3.4
17
20
255
51
43
240
48
41
225
45
38
225
45
38
90
18
15
110
22
19
10
15
Unit
MHz
t
PLH
, t
PHL
ns
t
PLH
, t
PHL
ns
t
PLZ
, t
PHZ
ns
t
PZL
, t
PZH
ns
t
TLH
, t
THL
ns
t
TLH
, t
THL
ns
C
IN
C
OUT
pF
pF
Typical @25°C,V
CC
=5.0 V
240
pF
SLS
System Logic
Semiconductor
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
