SL74HC4015
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
f
max
Parameter
Maximum Clock Frequency (50% Duty Cycle)
(Figure 2)
Maximum Propagation Delay, Clock to Q (Figures
2 and 5)
Maximum Propagation Delay, Reset to Q (Figures
1 and 5)
Maximum Output Transition Time, Any Output
(Figures 3 and 5)
Maximum Input Capacitance
Power Dissipation Capacitance (Per Latch)
C
PD
Used to determine the no-load dynamic power
consumption: P
D
=C
PD
V
CC2
f+I
CC
V
CC
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
-
Guaranteed Limit
25
°C
to
-55°C
6
30
35
175
35
30
205
41
35
75
15
13
10
≤85°C
4.8
24
28
220
44
37
255
51
43
95
19
16
10
≤125°C
4
20
24
265
53
45
310
62
53
110
22
19
10
Unit
MHz
t
PLH
, t
PHL
ns
t
PHL
ns
t
TLH
, t
THL
ns
C
IN
pF
Typical @25°C,V
CC
=5.0 V
140
pF
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
t
su
Parameter
Minimum Setup Time, D to Clock
(Figure 4)
Minimum Hold Time, Clock to D
(Figure 4)
Minimum Recovery Time, Reset to
Clock (Figure 1)
Minimum Pulse Width, Reset (Figure
1)
Minimum Pulse Width, Clock (Figure
4)
Maximum Input Rise and Fall Times
(Figure 1)
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Guaranteed Limit
25
°C
to
-55°C
50
10
9.0
5
5
5
5
5
5
80
16
14
80
16
14
1000
500
400
≤85°C
65
13
11
5
5
5
5
5
5
100
20
17
100
20
17
1000
500
400
≤125°C
75
15
13
5
5
5
5
5
5
120
24
20
120
24
20
1000
500
400
Unit
ns
t
h
ns
t
rec
ns
t
w
ns
t
w
ns
t
r
, t
f
ns
SLS
System Logic
Semiconductor
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
