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SL74HC4052D 参数 Datasheet PDF下载

SL74HC4052D图片预览
型号: SL74HC4052D
PDF下载: 下载PDF文件 查看货源
内容描述: 模拟多路复用器/多路解复用器(高性能硅栅CMOS ) [Analog Multiplexer/Demultiplexer(High-Performance Silicon-Gate CMOS)]
分类和应用: 解复用器
文件页数/大小: 9 页 / 90 K
品牌: SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
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SL74HC4052
ADDITIONAL APPLICATION CHARACTERISTICS
(GND = 0.0 V)
V
CC
Symbol
BW
Parameter
Maximum On-
Channel
Bandwidth or
Minimum
Frequency
Response
(Figure 5)
Off-Channel
Feedthrough
Isolation
(Figure 6)
Test Conditions
f
in
=1 MHz Sine Wave
Adjust f
in
Voltage to Obtain 0 dBm at V
OS
Increase f
in
Frequence Until dB Meter
Reads -3 dB
R
L
=50
Ω,
C
L
=10 pF
V
V
EE
V
Limit
*
25
°C
Unit
MHz
2.25
4.50
6.00
-2.25
-4.50
-6.00
95
95
95
-
f
in
= Sine Wave
Adjust f
in
Voltage to Obtain 0 dBm at V
IS
f
in
= 10 kHz, R
L
=600
Ω,
C
L
=50 pF
f
in
= 1.0 MHz, R
L
=50
Ω,
C
L
=10 pF
dB
2.25
4.50
6.00
2.25
4.50
6.00
-2.25
-4.50
-6.00
-2.25
-4.50
-6.00
-50
-50
-50
-40
-40
-40
mVpp
-
Feedthrough
Noise, Channel
Select Input to
Common O/I
(Figure 7)
V
IN
1 MHz Square Wave (t
r
= t
f
= 6 ns)
Adjust R
L
at Setup so that I
S
= 0 A Enable =
GND
R
L
=600
Ω,
C
L
=50 pF
2.25
4.50
6.00
2.25
4.50
6.00
2.25
4.50
6.00
2.25
4.50
6.00
-2.25
-4.50
-6.00
-2.25
-4.50
-6.00
-2.25
-4.50
-6.00
-2.25
-4.50
-6.00
25
105
135
35
145
190
dB
-50
-50
-50
-60
-60
-60
%
R
L
=10
Ω,
C
L
=10 pF
-
Crosstalk
Between Any
Two Switches
(Figure 14)
f
in
= Sine Wave
Adjust f
in
Voltage to Obtain 0 dBm at V
IS
f
in
= 10 kHz, R
L
=600
Ω,
C
L
=50 pF
f
in
= 1 MHz, R
L
=50
Ω,
C
L
=10 pF
THD
Total Harmonic
Distortion
(Figure 16)
f
in
= 1 kHz, R
L
=10 kΩ, C
L
=50 pF
THD = THD
Measured
- THD
Source
V
IS
=4.0 V
PP
sine wave
V
IS
=8.0 V
PP
sine wave
V
IS
=11.0 V
PP
sine wave
2.25
4.50
6.00
-2.25
-4.50
-6.00
0.10
0.08
0.05
* Limits not tested. Determined by design and verified by qualification.
SLS
System Logic
Semiconductor