SL74HC533
Octal 3-State Inverting Transparent Latch
High-Performance Silicon-Gate CMOS
The SL74HC533 is identical in pinout to the LS/ALS533. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. The data appears as the
outputs in inverted form. When Latch Enable goes low, data meeting
the setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches,
but when Output Enable is high, all device outputs are forced to the
high-impedance state. Thus, data may be latched even when the
outputs are not enabled.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0
µA
•
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC533N Plastic
SL74HC533D SOIC
T
A
= -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Output
Enable
PIN 20=V
CC
PIN 10 = GND
L
L
L
H
Latch
Enable
H
H
L
X
D
H
L
X
X
Output
Q
L
H
no
change
Z
X = don’t care
Z = high impedance
System Logic
Semiconductor
SLS
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
