欢迎访问ic37.com |
会员登录 免费注册
发布采购

SL74HC651 参数 Datasheet PDF下载

SL74HC651图片预览
型号: SL74HC651
PDF下载: 下载PDF文件 查看货源
内容描述: 八路三态总线收发器和D触发器(高性能硅栅CMOS ) [Octal 3-State Bus Transceivers and D Flip-Flops(High-Performance Silicon-Gate CMOS)]
分类和应用: 总线收发器触发器
文件页数/大小: 9 页 / 82 K
品牌: SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
 浏览型号SL74HC651的Datasheet PDF文件第2页浏览型号SL74HC651的Datasheet PDF文件第3页浏览型号SL74HC651的Datasheet PDF文件第4页浏览型号SL74HC651的Datasheet PDF文件第5页浏览型号SL74HC651的Datasheet PDF文件第6页浏览型号SL74HC651的Datasheet PDF文件第7页浏览型号SL74HC651的Datasheet PDF文件第8页浏览型号SL74HC651的Datasheet PDF文件第9页  
SL74HC651
Octal 3-State Bus Transceivers and D Flip-Flops
High-Performance Silicon-Gate CMOS
The SL74HC651 is identical in pinout to the LS/ALS651. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
These devices consists of bus transceiver circuits, D-type flip-flop,
and control circuitry arranged for multiplex transmission of data
directly from the data bus or from the internal storage registers.
Direction and Output Enable are provided to select the read-time or
stored data function. Data on the A or B Data bus, or both, can be
stored in the internal D flip-flops by low-to-high transitions at the
appropriate clock pins (A-to-B Clock or B-to-A Clock) regardless of the
select or enable or enable control pins. When A-to-B Source and B-to-
A Source are in the real-time transfer mode, it is als o possible to store
data without using the internal D-type flip-flops by simulta-neously
enabling Direction and Output Enable. In this configuration each
output reinforces its input. Thus, when all other data sources to the
two sets of bus lines are at high impedance, each set of bus lines will
remain at its last state.
The SL74HC651 has inverted outputs.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
µA
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC651N Plastic
SL74HC651D SOIC
T
A
= -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 24=V
CC
PIN 12 = GND
SLS
System Logic
Semiconductor