SL74HCT163
AC ELECTRICAL CHARACTERISTICS
(V
CC
=5.0 V
±
10%, C
L
=50pF,Input t
r
=t
f
=6.0 ns)
Guaranteed Limit
Symbol
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
TLH
, t
THL
C
IN
Maximum Propagation Delay, Clock to Ripple
Carry Out (Figures 1,6)
Maximum Output Transition Time, Any Output,
(Figures 1 and 6)
Maximum Input Capacitance
Power Dissipation Capacitance (Per Gate)
C
PD
Used to determine the no-load dynamic power
consumption: P
D
=C
PD
V
CC2
f+I
CC
V
CC
+∆I
CC
V
CC
Parameter
Maximum Clock Frequency (Figures 1,6)
Maximum Propagation Delay, Clock to Q
(Figures 1,6)
Maximum Propagation Delay, Enable T to Ripple
Carry Out (Figures 2,6)
25
°C
to
-55°C
30
34
41
32
39
35
43
15
10
≤85°C
24
43
51
40
49
44
54
19
10
≤125°C
20
51
62
48
59
53
65
22
10
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
pF
Typical @25°C,V
CC
=5.0 V
60
pF
TIMING REQUIREMENTS
(V
CC
=5.0 V
±
10%, C
L
=50pF,Input t
r
=t
f
=6.0 ns)
Guaranteed Limit
Symbol
t
su
t
su
t
su
t
su
t
h
t
h
t
h
t
h
t
rec
t
w
t
w
t
r,
t
f
Parameter
Minimum Setup Time, Preset Data Inputs to Clock
(Figure 4)
Minimum Setup Time, Load to Clock (Figure 4)
Minimum Setup Time, Reset to Clock (Figure 3)
Minimum Setup Time, Enable T or Enable P to Clock
(Figure 5)
Minimum Hold Time, Clock to Preset Data Inputs
(Figure 4)
Minimum Hold Time, Clock to Load (Figure 4)
Minimum Hold Time, Clock to Reset (Figure 3)
Minimum Hold Time, Clock to Enable T or Enable P
(Figure 5)
Minimum Recovery Time, Load Inactive to Clock
(Figure 4)
Minimum Pulse Width, Clock (Figure 1)
Minimum Pulse Width, Reset (Figure 4)
Maximum Input Rise and Fall Times (Figure 1)
25
°C
to
-55°C
30
27
32
40
10
3
3
3
25
16
16
500
≤85°C
38
34
40
50
13
3
3
3
31
20
20
500
≤125°C
45
41
48
60
15
3
3
3
38
24
24
500
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SLS
System Logic
Semiconductor
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
