SL74LV374
OCTAL D-TIME FLIP-FLOP; POSITIVE EDGE-
TRIGGER (3-StatE)
SL74LV374 are compatible by pinning with SL74HC374 and
SL74HCT374 series. Input voltage levels are compatible with
standard CMOS levels.
•
Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL IC
S
.
•
Supply voltage range from 2.0 to 3.2 V
•
LOW input current: 1.0
µÀ;
0.1
µÀ
at Ò = 25
°Ñ
•
Output current 8 mÀ
•
Latch current value not less than 150 mÀ at Ò = 125
°Ñ
•
ESD acceptable values: not less than 2000 V as per HBM,
and not less than 200 V as per MM
ORDERING INFORMATION
SL74LV374N Plastic DIP
SL74LV374D SOIC
T
A
= -40° to 125° C
for all packages
BLOCK DIAGRAM
03
04
07
08
13
14
17
18
11
02
05
06
09
12
15
16
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CP
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
OE
Q
0
D
0
D
1
Q
1
Q
2
D
2
D
3
Q
3
PIN ASSIGNMENT
01
02
03
04
05
20
19
18
17
16
V
CC
Q
7
D
7
D
6
Q
6
Q
5
D
5
D
4
Q
4
CP
374
06
07
08
09
10
15
14
13
12
11
19
Q
7
OE
01
GND
Pin 20=V
CC
Pin 10 = GND
FUNCTION TABLE
Inputs
OE
L
L
L
H
CP
Dn
H
L
X
X
Output
Qn
H
L
no change
Z
L, H,
X
SLS
System Logic
Semiconductor
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
