SL74LV573
OCTAL D-TYPE TRANSPARENT LATCH (3-State)
By pinning SL74LV573 are compatible with SL74HC573 and
SL74HCT573 series. Input voltage levels are compatible with
stadard CMOS levels.
•
Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL IC
S
•
Voltage supply range from 1.2 to 5.5 V
•
LOW input current: 1.0
µÀ;
0.1
µÀ
at Ò = 25
°Ñ
•
Output current 8 mÀ
•
Latch current: not less than150 mÀ at Ò = 125
°Ñ
•
ESD acceptable value: not less than 2000 V as per HBM and
not less than 200 V as per MM
ORDERING INFORMATION
SL74LV573N Plastic DIP
SL74LV573D SOIC
T
A
= -40° to 125° C
for all packages
FUNCTION TABLE
Inputs
OE
L
L
L
H
LE
H
H
L
X
D
H
L
X
X
Outputs
Q
H
L
no change
Z
PIN ASSIGNMENT
OE
D0
D1
D2
D3
D4
D5
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LE
H -HIGH voltage level
L - LOW voltage level
X - don’t care
Z - High impedance state
D6
D7
GND
SLS
System Logic
Semiconductor
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
