DESCRIPTION OF PIN FUNCTIONS
BUFFER
QFP/
TQFP
PIN NO.
TYPE
NAME
SYMBOL
DESCRIPTION
HOST PROCESSOR INTERFACE
48-51 Data Bus 0-7
53-56
D0-D7
The data bus connection used by the host
microprocessor to transmit data to and from
I/O24
the chip.
These pins are in a high-
impedance state when not in the output
mode.
44
45
46
nI/O Read
nI/O Write
nIOR
I
I
I
This active low signal is issued by the host
microprocessor to indicate a read operation.
nIOW
This active low signal is issued by the host
microprocessor to indicate a write operation.
Address Enable AEN
Active high Address Enable indicates DMA
operations on the host data bus. Used
internally to qualify appropriate address
decodes.
28-34 I/O Address
A0-A10
I
These host address bits determine the I/O
address to be accessed during nIOR and
41-43,
97
nIOW cycles.
These bits are latched
internally by the leading edge of nIOR and
nIOW. All internal address decodes use the
full A0 to A10 address bits.
21,52, DMA Request
DRQ_A
DRQ_B
DRQ_C
This active high output is the DMA request
for byte transfers of data between the host
and the chip. This signal is cleared on the
last byte of the data transfer by the nDACK
signal going low (or by nIOR going low if
nDACK was already low as in demand
mode).
O24
99
A, B, C
22,36, nDMA
nDACK_A
nDACK_B
nDACK_C
I
I
An active low input acknowledging the
request for a DMA transfer of data between
the host and the chip. This input enables
the DMA read or write internally.
96
Acknowledge
A, B, C
35
Terminal Count
TC
This signal indicates to the chip that DMA
data transfer is complete.
TC is only
accepted when nDACK_x is low. In AT and
PS/2 model 30 modes, TC is active high
and in PS/2 mode, TC is active low.
6
SMSC [ SMSC CORPORATION ]
