Multiple Channel 1°C Temperature Sensors with Beta Compensation
Datasheet
Table 7.19 Substrate Diode Ideality Factor Look-Up Table (BJT Model) (continued)
SETTING
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
FACTOR
0.9960
0.9973
0.9986
1.0000
1.0013
1.0026
1.0039
1.0053
1.0066
SETTING
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
FACTOR
1.0173
1.0187
1.0200
1.0213
1.0226
1.0239
1.0252
1.0265
1.0278
SETTING
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
FACTOR
1.0382
1.0395
1.0408
1.0421
1.0434
1.0447
1.0460
1.0473
1.0486
APPLICATION NOTE:
When measuring a 65nm Intel CPU, the Ideality Setting should be the default 12h. When
measuring a 45nm Intel CPU, the Ideality Setting should be 15h.
7.15
High Limit Status Register
Table 7.20 High Limit Status Register
ADDR.
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
35h
R-C
High Limit
Status
-
-
-
-
E3HIGH
E2HIGH
E1HIGH
IHIGH
00h
The High Limit Status Register contains the status bits that are set when a temperature channel high
limit is exceeded. If any of these bits are set, then the HIGH status bit in the Status Register is set.
Reading from the High Limit Status Register will clear all bits if. Reading from the register will also
clear the HIGH status bit in the Status Register.
The ALERT pin will be set if the programmed number of consecutive alert counts have been met and
any of these status bits are set.
The status bits will remain set until read unless the ALERT pin is configured as a comparator output
(see
Bit 3 - E3HIGH (EMC1414 only) - This bit is set when the External Diode 3 channel exceeds its
programmed high limit.
Bit 2 - E2HIGH - This bit is set when the External Diode 2 channel exceeds its programmed high limit.
Bit 1 - E1HIGH - This bit is set when the External Diode 1 channel exceeds its programmed high limit.
Bit 0 - IHIGH - This bit is set when the Internal Diode channel exceeds its programmed high limit.
Revision 1.41 (02-23-12)
40
SMSC EMC1413 / EMC1414
DATASHEET
SMSC [ SMSC CORPORATION ]
