RPM-Based Fan Controller with HW Thermal Shutdown
Datasheet
6.9
Critical Temperature Limit Registers
Table 6.13 Limit Registers
ADDR
19h
1Ah
1Bh
1Dh
R/W
R/W
once
R/W
once
R/W
once
R/W
once
REGISTER
External Diode
1 Tcrit Limit
External Diode
2 Tcrit Limit
External Diode
3 Tcrit Limit
Internal Diode
Tcrit Limit
B7
Sign
Sign
Sign
Sign
B6
64
64
64
64
B5
32
32
32
32
B4
16
16
16
16
B3
8
8
8
8
B2
4
4
4
4
B1
2
2
2
2
B0
1
1
1
1
DEFAULT
64h
(+100°C)
64h
(+100°C)
64h
(+100°C)
64h
(+100°C)
The Critical Temperature Limit Registers store the Critical Temperature Limit. At power up, none of the
respective channels are linked to the SYS_SHDN pin or the Hardware set Thermal/Critical Shutdown
circuitry.
Whenever one of the registers is updated, two things occur. First, the register is locked so that it cannot
be updated again without a power on reset. Second, the respective temperature channel is linked to
the SYS_SHDN pin and the Hardware set Thermal/Critical Shutdown Circuitry. At this point, if the
measured temperature channel exceeds the Critical limit, the SYS_SHDN pin will be asserted, the
appropriate bit set in the Tcrit Status Register, and the TCRIT bit in the Interrupt Status Register will
be set.
6.10
Configuration Register
Table 6.14 Configuration Register
ADDR
20h
R/W
R/W
REGISTER
Configuration
B7
MASK
-
B6
-
B5
-
B4
B3
SYS3
B2
SYS2
B1
SYS1
B0
APD
DEFAULT
00h
The Configuration Register controls the basic functionality of the EMC2103. The bits are described
below.
Bit 7 - MASK - Blocks the ALERT pin from being asserted.
‘0’ (default) - The ALERT pin is unmasked. If any bit in either status register is set, the ALERT pin
will be asserted (unless individually masked via the Mask Register)
‘1’ - The ALERT pin is masked and will not be asserted.
Bit 3 - SYS3 (EMC2103-2 only) - Enables the high temperature limit for the External Diode 3 channel
to trigger the Critical / Thermal Shutdown circuitry (see
‘0’ (default) - the External Diode 3 channel high limit will not be linked to the SYS_SHDN pin. If the
temperature meets or exceeds the limit, the ALERT pin will be asserted normally.
‘1’ - the External Diode 3 channel high limit will be linked to the SYS_SHDN pin. If the temperature
meets or exceeds the limit then the SYS_SHDN pin will be asserted. The SYS_SHDN# pin will be
released when the temperature drops below the high limit. The ALERT pin will be asserted
normally.
Bit 2 - SYS2 (EMC2103-2 only) - Enables the high temperature limit for the External Diode 2 channel
to trigger the Critical / Thermal Shutdown circuitry (see
SMSC EMC2103
47
Revision 0.85 (01-29-08)
DATASHEET
SMSC [ SMSC CORPORATION ]
