Dual RPM-Based PWM Fan Controller with Hardware Thermal Shutdown
Datasheet
Table 6.1 EMC2104 Register Set (continued)
REGISTER
NAME
Muxed Pin
Configuration
Register
GPIO Direction
Register
GPIO Output
Configuration
Register
GPIO Input
Register
GPIO Output
Register
GPIO Interrupt
Enable Register
GPIO Status
DEFAULT
VALUE
ADDR
R/W
FUNCTION
Controls the pin function for the pins
muxed with PWMs or GPIOs
Controls the GPIO direction for GPIOs 1
-4
Controls the output type GPIOs 1 - 4
LOCK
PAGE
E0h
R/W
01h
No
E1h
R/W
00h
No
E2h
R/W
00h
No
E3h
E4h
E5h
E6h
R
R/W
R/W
R
Stores the inputs for GPIOs 1 - 4
Controls the output state of GPIOs 1 - 4
Enabled Interrupts for GPIOs 1 - 4
Indicates change of state for inputs on
GPIOs 1 - 4
Lock Register
00h
00h
00h
00h
No
No
No
No
EF
R/W
Software Lock
Locks all SWL registers
Revision Registers
00h
SWL
FCh
FDh
FEh
FFh
R
R
R
R
Product Features
Product ID
Manufacturer ID
Revision
Stores information about which pin
controlled product features are set
Stores the unique Product ID
Stores the Manufacturer ID
Revision
00h
1Dh
5Dh
02h
No
No
No
No
During Power-On-Reset (POR), the default values are stored in the registers. A POR is initiated when
power is first applied to the part and the voltage on the VDD supply surpasses the POR level as
specified in the electrical characteristics. Any reads to undefined registers will return 00h. Writes to
undefined registers will not have an effect.
6.1.1
Lock Entries
The Lock Column describes the locking mechanism, if any, used for individual registers. All SWL
registers are Software Locked and therefore made read-only when the LOCK bit is set.
SMSC EMC2104
49
Revision 1.74 (05-08-08)
DATASHEET
SMSC [ SMSC CORPORATION ]
