RPM-Based PWM Fan Controller
Datasheet
5.17
TACH Target Registers
Table 5.27 TACH Target Registers
ADDR
3Ch
3Dh
R/W
R/W
R/W
REGISTER
TACH Target
Low Byte
TACH Target
High Byte
B7
16
4096
B6
8
2048
B5
4
1024
B4
2
512
B3
1
256
B2
-
128
B1
-
64
B0
-
32
DEFAULT
F8h
FFh
The TACH Target Registers hold the target tachometer value that is maintained by the RPM-based
Fan Speed Control Algorithm.
The value in the TACH Target Registers will always reflect the current TACH Target value.
If the algorithm is enabled, setting the TACH Target Register to FFh will disable the fan driver (set the
fan drive setting to 0%). Setting the TACH Target to any other value (from a setting of FFh) will cause
the algorithm to invoke the Spin Up Routine after which it will function normally.
The Tach Target is not applied until the high byte is written. Once the high byte is written, the current
value of both high and low bytes will be used as the next Tach target.
5.18
TACH Reading Registers
Table 5.28 TACH Reading Registers
ADDR
3Eh
3Fh
R/W
R
R
REGISTER
Fan TACH
Fan TACH
Low Byte
B7
4096
16
B6
2048
8
B5
1024
4
B4
512
2
B3
256
1
B2
128
-
B1
64
-
B0
32
-
DEFAULT
FFh
F8h
The TACH Reading Registers’ contents describe the current tachometer reading for the fan. By default,
the data represents the fan speed as the number of 32kHz clock periods that occur for a single
revolution of the fan.
shows the detailed conversion from TACH measurement (COUNT) to RPM while
shows the simplified translation of TACH Reading Register count to RPM assuming a 2-pole fan,
measuring 5 edges, with a frequency of 32.768kHz. These equations are solved and tabulated for ease
of use in
AN17.4 RPM to TACH Counts Conversion.
Whenever the high byte register is read, the corresponding low byte data will be loaded to internal
shadow registers so that when the low byte is read, the data will always coincide with the previously
read high byte.
Revision 1.1 (10-12-09)
36
SMSC EMC2301
DATASHEET
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