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KBD42W11 参数 Datasheet PDF下载

KBD42W11图片预览
型号: KBD42W11
PDF下载: 下载PDF文件 查看货源
内容描述: 键盘控制器被编程,以支持 [Keyboard controller is programmed to support]
分类和应用: 控制器
文件页数/大小: 16 页 / 101 K
品牌: SMSC [ SMSC CORPORATION ]
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STATUS REGISTER
The status register is an 8-bit read-only register at I/O address hex 64 that holds information about the
state of the keyboard controller and interface. It may be read at any time.
BIT
0
1
2
BIT DESCRIPTION
Output Buffer Full
Input Buffer Full
System Flag
FUNCTION
0: Output Buffer Empty
1: Output Buffer Full
0: Input Buffer Empty
1: Input Buffer Full
This bit may be set to 0 or 1 by writing to the system flag bit in
the command byte of the keyboard controller. It is set to 0 after a
power-on reset
0: Data Byte
1: Command Byte
0: Keyboard is Inhibited
1: Keyboard is Not Inhibited
0: No Transmit Time Out Error
1: Transmit Time Out Error
0: No Receive Time Out Error
1: Receive Time Out Error
0: Odd Parity (No Error)
1: Even Parity (Error)
3
4
5
6
7
Command/data
Inhibit Switch
Transmit Time Out
Receive Time Out
Parity Error
OUTPUT BUFFER
The output buffer is an 8-bit read-only register at I/O address hex 60. The keyboard controller uses the
output buffer to send the scan code received from the keyboard and data bytes required by command to
the system. The output buffer should be read only when the output buffer full bit in the register is 1.
INPUT BUFFER
The input buffer is an 8-bit write-only register at I/O address hex 60 or 64. Writing to address hex 60
sets a flag that indicates a data write; writing to address hex 64 sets a flag that indicates a command
write. Data written to I/O address hex 60 are sent to the keyboard (unless the keyboard controller is
expecting a data byte) following the controller's input buffer only if the input buffer full bit in the status
register is set to 0.
I/O PORTS
The keyboard controller has two 8-bit I/O ports and two test inputs. One of the ports is assigned for
input and the other for output. The controller uses the test inputs to read the state of the keyboard's
clock line and data line.
10