TQFP PIN NO.
206
184
189,188,186,185
4
204
203
200
202
19
17
14
21
22
20
8
11
NAME
RX_CLK
CRS
RXD[3:0]
COL
RX_DV
RX_ER
MCLK
MDATA
694nLNK
694nEN
CLK25IN
GPIO1
GPIO2
TEST
X20
BIAS
I/O
I
TTL4
I
TTL4
I
TTL4
I
TTL4
I
TTL4
I
TTL4
O
TTL4
IO
TTL4
I
TTL4
O
TTL4
I
TTL4
IO
TTL4
IO
TTL4
I
TTL4
O
TTL4
I
DESCRIPTION
MII Receive Clock
MII Carrier Sense
MII Receive Data
MII Collision Signal
MII Receive Data Valid Signal
MII Receive Error Signal
MII Management Interface Clock
MII Management Interface Data
10Base-T Link Integrity Status
694 Enable. Tri-States 694 Outputs when
PHY100 is in use
System Clock (25MHz) Input
General Purpose I/O
General Purpose I/O
Used for In-Circuit Device Test
20MHz Buffered Clock Output
Bias Current Input for Clock Multiplier.
1
Connect a 6K
Ω
/
8
w 1% Resistor between
RBIAS and Ground
Regulated Voltage Input for Clock
Multiplier
Reset Output to Physical Layer Chip
Physical Layer Power-Down Control
Physical Layer Power-Down Control
MODEM RESET
MODEM chip select
MODEM ready/busy signal. Ready when
high
MODEM Interrupt request
MODEM Power Down
MODEM Power Down Control
MODEM Ring-in signal
MODEM Ring-out signal
CardBus status changed signal
12
199
15
6
179
176
166
168
180
181
170
178
50
ZENER
PHYRST
nPHY_PWRDWN
FETPWR_PHY
nRESETM
nCSM
RDYM
IREQM
POWERDWNM
FETPWRM
RINGIN
RINGOUT
STATCHG
I
O
TTL4
O
TTL4
O
TTL4
O
TTL4
O
TTL4
I
TTL4
I
TTL4
O
TTL4
O
TTL4
I
TTL4
O
TTL4
O
TTL4
7
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