High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
Table 3.4 Configuration Inputs
PIN NO.
2
20
19
17
16
6
SIGNAL NAME
PHYAD4
PHYAD3
PHYAD2
PHYAD1
PHYAD0
MODE2
I
I
I
I
I
I
TYPE
DESCRIPTION
PHY Address Bit 4:
set the default address of the PHY.
PHY Address Bit 3:
set the default address of the PHY.
PHY Address Bit 2:
set the default address of the PHY.
PHY Address Bit 1:
set the default address of the PHY.
PHY Address Bit 0:
set the default address of the PHY.
PHY Operating Mode Bit 2:
set the default MODE of the
PHY. See
for the MODE options.
PHY Operating Mode Bit 1:
set the default MODE of the
PHY. See
for the MODE options.
PHY Operating Mode Bit 0:
set the default MODE of the
PHY. See
for the MODE options.
Test Mode Select 1:
Must be left floating.
Test Mode Select 0:
Must be left floating.
Internal +1.8V Regulator Enable:
+3.3V – Enables internal regulator.
0V – Disables internal regulator.
5
MODE1
I
4
MODE0
I
10
9
12
TEST1
TEST0
REG_EN
I
I
I
Table 3.5 General Signals
PIN NO.
46
25
23
22
11
nINT
nRST
CLKIN/XTAL1
XTAL2
CLK_FREQ
SIGNAL NAME
TYPE
OD
I
I
O
I
DESCRIPTION
LAN Interrupt
– Active Low output.
External Reset
– input of the system reset. This signal is
active LOW.
Clock Input
– 25 MHz external clock or crystal input.
Clock Output
– 25 MHz crystal output.
Clock Frequency
– define the frequency of the input
clock CLKIN
0 – Clock frequency is 25 MHz.
1 – Reserved.
This input needs to be held low continuously, during and
after reset. This pin should be pulled-down to VSS via a
pull-down resistor.
64
3
2
NC1
GPO2
GPO1
O
O
No Connect
General Purpose Output 2 –
General Purpose Output
signal Driven by bits in registers 27 and 31.
General Purpose Output 1 –
General Purpose Output
signal Driven by bits in registers 27 and 31.
(Muxed with PHYAD4 signal)
7
Rev. 0.6 (12-12-03)
SMSC LAN83C185
DATASHEET
SMSC [ SMSC CORPORATION ]
