High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
Table 5.40 Register 6 - Auto Negotiation Expansion
ADDRESS
6.15:5
6.4
6.3
6.2
6.1
6.0
NAME
Reserved
Parallel Detection
Fault
Link Partner Next
Page Able
Next Page Able
Page Received
Link Partner Auto-
Negotiation Able
1 = fault detected by parallel detection logic
0 = no fault detected by parallel detection logic
1 = link partner has next page ability
0 = link partner does not have next page ability
1 = local device has next page ability
0 = local device does not have next page ability
1 = new page received
0 = new page not yet received
1 = link partner has auto-negotiation ability
0 = link partner does not have auto-negotiation ability
DESCRIPTION
MODE
RO
RO/
LH
RO
RO
RO/
LH
RO
DEFAULT
0
0
0
0
0
0
Table 5.41 Register 16 - Silicon Revision
ADDRESS
16.15:10
16.9:6
16.5:0
NAME
Reserved
Silicon Revision
Reserved
Four-bit silicon revision identifier.
DESCRIPTION
MODE
RO
RO
RO
DEFAULT
0
0001
0
Table 5.42 Register 17 - Mode Control/Status
ADDRESS
17.15
17.14
NAME
Reserved
FASTRIP
DESCRIPTION
Write as 0; ignore on read.
10Base-T fast mode:
0 = normal operation
1 = Reserved
Must be left at 0
Enable the Energy Detect Power-Down mode:
0 = Energy Detect Power-Down is disabled
1 = Energy Detect Power-Down is enabled
Write as 0, ignore on read
The Low_Squelch signal is equal to LOWSQEN AND
EDPWRDOWN.
Low_Squelch = 1 implies a lower threshold
(more sensitive).
Low_Squelch = 0 implies a higher threshold
(less sensitive).
Management Data Preamble Bypass:
0 – detect SMI packets with Preamble
1 – detect SMI packets without preamble
Reserved
Must be left at 0
MODE
RW
RW,
NASR
DEFAULT
0
0
17.13
EDPWRDOWN
RW
0
17.12
17.11
Reserved
LOWSQEN
RW
RW
0
0
17.10
MDPREBP
RW
0
17.9
Reserved
RW
0
SMSC LAN83C185
DATASHEET
33
Rev. 0.6 (12-12-03)
SMSC [ SMSC CORPORATION ]
