High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
The encoding process may be bypassed by clearing bit 6 of register 31. When the encoding is
bypassed the 5th transmit data bit is equivalent to TX_ER.
Note that encoding can be bypassed only when the MAC interface is configured to operate in MII
mode.
Table 4.1 4B/5B Code Table
CODE
RECEIVER
TRANSMITTER
GROUP
SYM
INTERPRETATION
INTERPRETATION
11110
01001
10100
10101
01010
01011
01110
01111
10010
10011
10110
10111
11010
11011
11100
11101
11111
11000
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
I
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
DATA
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
DATA
IDLE
Sent after /T/R until TX_EN
Sent for rising TX_EN
J
First nibble of SSD, translated to “0101”
following IDLE, else RX_ER
10001
01101
K
T
Second nibble of SSD, translated to
“0101” following J, else RX_ER
Sent for rising TX_EN
Sent for falling TX_EN
First nibble of ESD, causes de-assertion
of CRS if followed by /R/, else assertion
of RX_ER
00111
R
Second nibble of ESD, causes
deassertion of CRS if following /T/, else
assertion of RX_ER
Sent for falling TX_EN
00100
00110
11001
00000
00001
H
V
V
V
V
Transmit Error Symbol
Sent for rising TX_ER
INVALID
INVALID, RX_ER if during RX_DV
INVALID, RX_ER if during RX_DV
INVALID, RX_ER if during RX_DV
INVALID, RX_ER if during RX_DV
INVALID
INVALID
INVALID
Rev. 0.8 (11-16-04)
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