LAN9118
High Performance
Single-Chip 10/100 Non-
PCI Ethernet Controller
PRODUCT FEATURES
Highlights
Optimized for the highest data-rate applications such
as high-definition video and multi-media applications
Efficient architecture with low CPU overhead
Easily interfaces to most 32-bit and 16-bit embedded
CPU’s
Integrated PHY
Supports audio & video streaming over Ethernet:
multiple high-definition (HD) MPEG2 streams
Pin compatible with other members of LAN9118
family (LAN9117, LAN9116 and LAN9115)
Reduced Power Modes
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Numerous power management modes
Wake on LAN*
Magic packet wakeup*
Wakeup indicator event signal
Link Status Change
Fully compliant with IEEE 802.3/802.3u standards
Integrated Ethernet MAC and PHY
10BASE-T and 100BASE-TX support
Full- and Half-duplex support
Full-duplex flow control
Backpressure for half-duplex flow control
Preamble generation and removal
Automatic 32-bit CRC generation and checking
Automatic payload padding and pad removal
Loop-back modes
One 48-bit perfect address
64 hash-filtered multicast addresses
Pass all multicast
Promiscuous mode
Inverse filtering
Pass all incoming with status report
Disable reception of broadcast packets
Datasheet
Single chip Ethernet controller
Target Applications
Video distribution systems, multi-room PVR
High-end Cable, satellite, and IP set-top boxes
Digital video recorders
High definition televisions
Digital media clients/servers
Home gateways
Flexible address filtering modes
Key Benefits
Supports highest performance applications
— Highest performing non-PCI Ethernet controller in the
market
— 32-bit interface with fast bus cycle times
— Burst-mode read support
Integrated Ethernet PHY
— Auto-negotiation
— Automatic polarity detection and correction
High-Performance host bus interface
— Simple, SRAM-like interface
— 32/16-bit data bus
— Large, 16Kbyte FIFO memory that can be allocated to
RX or TX functions
— One configurable host interrupt
Eliminates dropped packets
— Internal buffer memory can store over 200 packets
— Supports automatic or host-triggered PAUSE and back-
pressure flow control
Miscellaneous features
— Low profile 100-pin, TQFP lead-free RoHS Compliant
package
— Integral 1.8V regulator
— General Purpose Timer
— Support for optional EEPROM
— Support for 3 status LEDs multiplexed with
Programmable GPIO signals
Minimizes CPU overhead
— Supports Slave-DMA
— Interrupt Pin with Programmable Hold-off timer
Reduces system cost and increases design flexibility
— SRAM-like interface easily interfaces to most
embedded CPU’s or SoC’s
— Low-cost, low--pin count non-PCI interface for
embedded designs
3.3V Power Supply with 5V tolerant I/O
0 to 70°C
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Third-party brands and names are the property of their respective
owners.
SMSC LAN9118
DATASHEET
Revision 1.3 (05-31-07)
SMSC [ SMSC CORPORATION ]
