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LAN91C100FD 参数 Datasheet PDF下载

LAN91C100FD图片预览
型号: LAN91C100FD
PDF下载: 下载PDF文件 查看货源
内容描述: 筵席快速以太网控制器,全双工能力 [FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY]
分类和应用: 控制器以太网以太网:16GBASE-T
文件页数/大小: 68 页 / 421 K
品牌: SMSC [ SMSC CORPORATION ]
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DESCRIPTION OF PIN FUNCTIONS
PQFP/TQFP
PIN NO.
202
1
NAME
Loopback
nLink
Status
nFullstep
SYMBOL
LBK
nLNK
BUFFER
TYPE
O4
I with
pullup
O4
DESCRIPTION
Output. Active when LOOP bit is set (TCR bit 1).
Independent of port selection (MIISEL=X).
Input. General purpose input port used to convey
LINK status (EPHSR bit 14). Independent of port
selection (MIISEL=X).
Output. Non volatile output pin. Driven by inverse
of FULLSTEP (CONFIG bit 10). Independent of
port selection (MIISEL=X).
Output. Non volatile output pin. Driven by MII
SELECT (CONFIG bit 15). High indicates the MII
port is selected, low indicates the 10 Mbps ENDEC
is selected.
Output. Non volatile output pin. Driven by AUI
SELECT (CONFIG bit 8). Independent of port
selection (MIISEL= X).
Output to MII PHY. Envelope to 100 Mbps
transmission. This pin stays low if MIISEL is low.
Input from MII PHY. Envelope of packet reception
used for deferral and backoff purposes. This pin is
ignored when MIISEL is low.
Input from MII PHY. Envelope of data valid
reception. Used for receive data framing. This pin
is ignored when MIISEL is low.
Input from MII PHY. Collision detection input. This
pin is ignored when MIISEL is low.
Outputs. Transmit Data nibble to MII PHY.
Input. Transmit clock input from MII. Nibble rate
clock (25 MHz). This pin is ignored when MIISEL
is low.
Input. Receive clock input from MII PHY. Nibble
rate clock. This pin is ignored when MIISEL is low.
Inputs. Received Data nibble from MII PHY.
These pins are ignored when MIISEL is low.
MII management data input.
195
nFSTEP
6
MII Select
MIISEL
O4
194
AUI Select
AUISEL
O4
30
19
12
Transmit
Enable
100 Mbps
Carrier
Sense 100
Mbps
Receive
Data Valid
Collision
Detect 100
Mbps
Transmit
Data
Transmit
Clock
Receive
Clock
Receive
Data
Manage-
ment Data
Input
Manage-
ment Data
Output
Manage-
ment Clock
Receive
Error
TXEN100
O12
CRS100
I with
pulldown
I with
pulldown
I with
pulldown
O12
I with
pullup
I with
pullup
I
I with
pulldown
O4
RX_DV
18
COL100
25, 26, 28,
29
9
TXD0-
TXD3
TX25
17
20, 21, 22,
24
198
RX25
RXD0-
RXD3
MDI
196
MDO
MII management data output.
192
11
MCLK
RX_ER
O4
I with
pulldown
MII management clock.
Input. Indicates a code error detected by PHY.
Used by the LAN91C100FD to discard the packet
being received. The error indication reported for
this event is the same as a bad CRC (Receive
Status Word bit 13). This pin is ignored when
MIISEL is low.
SMSC DS – LAN91C100FD REV. B
Page 8
Rev. 05/31/2000