LAN9211
High-Performance Small
Form Factor Single-Chip
Ethernet Controller with HP
Auto-MDIX
PRODUCT FEATURES
Highlights
Optimized for medium to high performance
applications
Efficient architecture with low CPU overhead
Easily interfaces to most 16-bit embedded CPU’s
Integrated PHY with HP Auto-MDIX
Integrated checksum offload engine helps reduce
CPU load
Low pin count and small body size package for small
form factor system designs
Supports audio & video streaming over Ethernet:
1-2 high-definition (HD) MPEG2 streams
Reduced Power Modes
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Numerous power management modes
Wake on LAN
Magic packet wakeup
Wakeup indicator event signal
Link Status Change
Fully compliant with IEEE 802.3/802.3u standards
Integrated Ethernet MAC and PHY
10BASE-T and 100BASE-TX support
Full- and Half-duplex support
Full-duplex flow control
Backpressure for half-duplex flow control
Preamble generation and removal
Automatic 32-bit CRC generation and checking
Automatic payload padding and pad removal
Loop-back modes
One 48-bit perfect address
64 hash-filtered multicast addresses
Pass all multicast
Promiscuous mode
Inverse filtering
Pass all incoming with status report
Disable reception of broadcast packets
Datasheet
Single chip Ethernet controller
Target Applications
Cable, satellite, and IP set-top boxes
Digital video recorders and DVD recorder/players
High definition televisions
Digital media clients/servers and home gateways
Video-over IP solutions, IP PBX & video phones
Wireless routers & access points
High-end audio distribution systems
Flexible address filtering modes
Integrated 10/100 Ethernet PHY
— Supports HP Auto-MDIX
— Auto-negotiation
— Supports energy-detect power down
Key Benefits
Non-PCI Ethernet controller formedium-high
performance sensitive applications
— Highest performing non-PCI Ethernet controller
— 16-bit interface with fast bus cycle times
— Burst-mode read support
High-Performance host bus interface
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Simple, SRAM-like interface
16-bit data bus
16Kbyte FIFO with flexible TX/RX allocation
One configurable host interrupt
Eliminates dropped packets
— Internal buffer memory can store over 200 packets
— Automatic PAUSE and back-pressure flow control
Miscellaneous features
— Small form factor, 56-pin QFN lead-free RoHS
Compliant package
— Integrated 1.8V regulator
— Integrated checksum offload engine
— Mixed endian support
— General Purpose Timer
— Optional EEPROM interface
— Support for 3 status LEDs multiplexed with
Programmable GPIO signals
Minimizes CPU overhead
— Supports Slave-DMA
— Interrupt Pin with Programmable Hold-off timer
Reduces system cost and increases design flexibility
SRAM-like interface easily interfaces to most
embedded CPU’s or SoC’s
Single 3.3V Power Supply with 5V tolerant I/O
0°C to +70°C Commercial Temperature Support
SMSC
LAN9211
DATASHEET
Revision 1.93 (11-27-07)
SMSC [ SMSC CORPORATION ]
