LAN9217
16-bit High-Performance
Single-Chip 10/100 Ethernet
Controller with HP Auto-MDIX
PRODUCT FEATURES
Highlights
Optimized for medium to high performance
applications
Efficient architecture with low CPU overhead
Easily interfaces to most 16-bit embedded CPU’s
Integrated PHY with HP Auto-MDIX
Supports audio & video streaming over Ethernet:
1-2 high-definition (HD) MPEG2 streams
Compatible with other members of LAN9218 family
Reduced Power Modes
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Numerous power management modes
Wake on LAN*
Magic packet wakeup*
Wakeup indicator event signal
Link Status Change
Datasheet
Single chip Ethernet controller
Fully compliant with IEEE 802.3/802.3u standards
Integrated Ethernet MAC and PHY
10BASE-T and 100BASE-TX support
Full- and Half-duplex support
Full-duplex flow control
Backpressure for half-duplex flow control
Preamble generation and removal
Automatic 32-bit CRC generation and checking
Automatic payload padding and pad removal
Loop-back modes
One 48-bit perfect address
64 hash-filtered multicast addresses
Pass all multicast
Promiscuous mode
Inverse filtering
Pass all incoming with status report
Disable reception of broadcast packets
Target Applications
Video distribution systems, multi-room PVR
Cable, satellite, and IP set-top boxes
Digital video recorders and DVD recorder/players
High definition televisions
Digital media clients/servers and home gateways
Video-over IP Solutions, IP PBX & video phones
Wireless routers & access points
High-end audio distribution systems
Flexible address filtering modes
Key Benefits
Non-PCI Ethernet controller for medium-high
performance applications
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Highest performing non-PCI Ethernet controller
16-bit interface with fast bus cycle times
Burst-mode read support
External MII Interface
Integrated 10/100 Ethernet PHY
— Supports HP Auto-MDIX
— Auto-negotiation
— Supports energy-detect power down
High-Performance host bus interface
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Simple, SRAM-like interface
16-bit data bus
16Kbyte FIFO with flexible TX/RX allocation
One configurable host interrupt
Low-profile, green, lead-free 100-pin TQFP package
Integrated 1.8V regulator
General Purpose Timer
Optional EEPROM interface
Support for 3 status LEDs multiplexed with
Programmable GPIO signals
Eliminates dropped packets
— Internal buffer memory can store over 200 packets
— Automatic PAUSE and back-pressure flow control
Miscellaneous features
Minimizes CPU overhead
— Supports Slave-DMA
— Interrupt Pin with Programmable Hold-off timer
Reduces system cost and increases design flexibility
SRAM-like interface easily interfaces to most
embedded CPU’s or SoC’s
Single 3.3V Power Supply with 5V tolerant I/O
0 to 70°C Commercial Temperature Support
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owners.
SMSC LAN9217
DATASHEET
Revision 1.5 (07-18-06)
SMSC [ SMSC CORPORATION ]
