Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
Chapter 12 GPIO/LED Controller
12.1
Functional Overview
The GPIO/LED Controller provides 6 configurable general purpose input/output pins, GPIO[5:0]. These
pins can be individually configured to function as inputs, push-pull outputs, or open drain outputs and
each is capable of interrupt generation with configurable polarity. Alternatively, all 6 GPIO pins can be
configured as LED outputs, enabling these pins to drive Ethernet status LEDs for external indication
of various attributes of the switch ports.
GPIO and LED functionality is configured via the GPIO/LED System Control and Status Registers
(CSRs). These registers are defined in Section 13.2.2, "GPIO/LED," on page 144.
12.2
GPIO Operation
The GPIO controller is comprised of 6 programmable input/output pins. These pins are individually
configurable via the GPIO CSRs. On application of a chip-level reset:
All GPIOs are set as inputs (GPIO Direction 5-0 (GPDIR[5:0]) cleared in General Purpose I/O Data
& Direction Register (GPIO_DATA_DIR))
All GPIO interrupts are disabled (GPIO Interrupt Enable[5:0] (GPIO[5:0]_INT_EN) cleared in
General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN)
All GPIO interrupts are configured to low logic level triggering (GPIO Interrupt Polarity 5-0
(GPIO_INT_POL[5:0]) cleared in General Purpose I/O Configuration Register (GPIO_CFG))
Note: GPIO[5:0] may be configured as LED outputs by default, dependant on the LED_en_strap[5:0]
configuration straps. Refer to Section 12.3, "LED Operation" for additional information.
The direction and buffer type of all 6 GPIOs are configured via the General Purpose I/O Configuration
Register (GPIO_CFG) and General Purpose I/O Data & Direction Register (GPIO_DATA_DIR). The
direction of each GPIO, input or output, should be configured first via its respective GPIO Direction 5-
0 (GPDIR[5:0]) bit in the General Purpose I/O Data & Direction Register (GPIO_DATA_DIR). When
configured as an output, the output buffer type for each GPIO is selected by the GPIO Buffer Type 5-
0 (GPIOBUF[5:0]) bits in the General Purpose I/O Configuration Register (GPIO_CFG). Push/pull and
open-drain output buffers are supported for each GPIO. When functioning as an open-drain driver, the
GPIO output pin is driven low when the corresponding GPIO Data 5-0 (GPIOD[5:0]) bit in the General
Purpose I/O Data & Direction Register (GPIO_DATA_DIR) is cleared to 0, and is not driven when set
to 1.
When a GPIO is enabled as a push/pull output, the value output to the GPIO pin is set via the
corresponding GPIO Data 5-0 (GPIOD[5:0]) bit in the General Purpose I/O Data & Direction Register
(GPIO_DATA_DIR). For GPIOs configured as inputs, the corresponding GPIO Data 5-0 (GPIOD[5:0])
bit reflects the current state of the GPIO input.
12.2.1
GPIO Interrupts
Each GPIO provides the ability to trigger a unique GPIO interrupt in the General Purpose I/O Interrupt
Status and Enable Register (GPIO_INT_STS_EN). Reading the GPIO Interrupt[5:0] (GPIO[5:0]_INT)
bits of this register provides the current status of the corresponding interrupt, and each interrupt is
enabled by setting the corresponding GPIO Interrupt Enable[5:0] (GPIO[5:0]_INT_EN) bit. The
GPIO/LED Controller aggregates the enabled interrupt values into an internal signal that is sent to the
System Interrupt Controller and is reflected via the Interrupt Status Register (INT_STS) GPIO Interrupt
Event (GPIO) bit. For more information on interrupts, refer to Chapter 5, "System Interrupts," on
page 55.
Revision 1.3 (08-27-09)
132
SMSC LAN9303/LAN9303i
DATASHEET
SMSC [ SMSC CORPORATION ]
