LPC47M172 参数 Datasheet PDF下载

Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

Chapter 1

General Description

The LPC47M172 is a 3.3V (5V tolerant) PC99a/PC2001 compliant Advanced I/O controller for Desktop

PCs. The device, which implements the Low Pin Count (LPC) interface, includes I/O functionality as well

as Motherboard GLUE logic into a 128-pin package. This is space saving solution on the motherboard

resulting in lower cost. The LPC47M172 also provides 13 general purpose pins, which offer flexibility to

the system designer, and two Fan Tachometer Inputs. The LPC47M172’s LPC interface supports LPC I/O

and DMA cycles.

The LPC47M172 includes complete legacy I/O: a keyboard interface with AMI

TM

BIOS; SMSC's true

CMOS 765B floppy disk controller with advanced digital data separator; two 16C550A compatible UARTs;

one Multi-Mode parallel port including ChiProtect circuitry plus EPP and ECP. The true CMOS 765B core

provides 100% compatibility with IBM PC/XT and PC/AT architectures; in addition, it provides data

overflow and underflow protection. The SMSC’s patented advanced digital data separator allows for ease

of testing and use. The parallel port is compatible with IBM PC/AT architecture, as well as IEEE 1284 EPP

and ECP. The LPC47M172 incorporates sophisticated power control circuitry (PCC) which includes

support for keyboard and mouse wake up events as well as PME support. The PCC supports multiple low

power-down modes. The LPC47M172 is ACPI 1.0b/2.0 compatible.

The Motherboard GLUE logic includes various power management logic; including generation of

nRSMRST, Power OK signal generation, 5V main and standby reference generation. There are also three

LEDs to indicate power status and hard drive activity. The translation circuit converts 3.3V signals to 5V

signals. Also included is SMBus main power well to resume power well isolation circuitry.

The LPC47M172 supports the ISA Plug-and-Play Standard register set (Version 1.0a). The I/O Address,

DMA Channel and hardware IRQ of each logical device in the LPC47M172 may be reprogrammed through

the internal configuration registers. There are up to 480 (960 for Parallel Port) I/O address location

options, a Serialized IRQ interface, and three DMA channels. On chip, Interrupt Generating Registers

enable external software to generate IRQ1 through IRQ15 on the Serial IRQ Interface.

The LPC47M172’s Enhanced Digital Data Separator does not require any external filter components and

is therefore easy to use and offers lower system costs and reduced board area. The LPC47M172 is

register compatible with SMSC’s proprietary 82077AA core.

This device utilizes two selectable (see Chapter 2) register sets; (1) standard SMSC and (2) tailored for

Intel reference designs. These register sets are detailed in Chapter 6 (Section 6.1).

SMSC/Non-SMSC Register Sets (Rev.

01-11-07)

Page 11

SMSC LPC47M172

DATASHEET