LPC47N252
ADVANCE INFORMATION
Advanced Notebook I/O Controller
with On-Board FLASH
FEATURES
3.3V Operation with 5V Tolerant Buffers
ACPI 1.1, PC99/PC2001 Compliant
LPC Interface with Clock Run Support
−
Serial IRQ Interface Compatible with
Serialized IRQ Support for PCI Systems
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15 Direct IRQs
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Four 8-Bit DMA Channels
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ACPI SCI Interface
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nSMI
−
Shadowed write only registers
Internal 64K Flash ROM
−
Programmed From Direct Parallel Interface,
8051, or LPC Host
−
2k-Byte Lockable Boot Block
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Can be Programmed Without 8051
Intervention
Three Power Planes
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Low Standby Current in Sleep Mode
−
Intelligent Auto Power Management for
Super I/O
ACPI Embedded Controller Interface
Configuration Register Set Compatible with ISA
Plug-and-Play Standard (Version 1.0a)
High-Performance Embedded 8051 Keyboard
and System Controller
−
Provides System Power Management
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System Watch Dog Timer (WDT)
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8042 Style Host Interface
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Supports Interrupt and Polling Access
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256 Bytes Data RAM
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On-Chip Memory-Mapped Control Registers
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Access to RTC and CMOS Registers
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Up to 16x8 Keyboard Scan Matrix
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Two 16 Bit Timer/Counters
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Integrated Full-Duplex Serial Port Interface
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Eleven 8051 Interrupt Sources
−
Thirty-Two 8-Bit, Host/8051 Mailbox
Registers
−
Thirty-six Maskable Hardware Wake-Up
Events
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Fast GATEA20
−
−
Fast CPU_RESET
Multiple Clock Sources and Operating
Frequencies
−
IDLE and SLEEP Modes
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Fail-Safe Ring Oscillator
Advanced Infrared Communications Controller
(IrCC 2.0)
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IrDA V1.2 (4Mbps), HPSIR, ASKIR,
Consumer IR Support
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Two IR Ports
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Relocatable Base I/O Address
Real-Time Clock
−
MC146818 and DS1287 Compatible
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256 Bytes of Battery Backed CMOS in Two
128-Byte Banks
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128 Bytes of CMOS RAM Lockable in 4x32
Byte Blocks
−
12 and 24 Hour Time Format
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Binary and BCD Format
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<2µA Standby Current (typ)
Two 8584-Style ACCESS.Bus Controllers
−
8051 Controlled Logic Allows ACCESS.Bus
Master or Slave Operation
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ACCESS.Bus Controllers are Fully
Operational on Standby Power
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2 Sets of Dedicated Pins per ACCESS.Bus
Controller
Four independent Hardware Driven PS/2 Ports
83 General Purpose I/O Pins
−
36 Maskable Hardware Wake-Event
Capable
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18 Programmable Open-Drain/Push-Pull
Outputs
−
16 Mapped into 8051 SFR Space
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24 LPC/8051-Addressable
Three Programmable Pulse-Width Modulator
Outputs
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Independent Clock Rates
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6 Bit Duty Cycle Granularity
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VCC1 and VCC2 operation mode
Dual Fan Tachometer Inputs
SMSC DB – LPC47N252
Rev. 10/27/2000
SMSC [ SMSC CORPORATION ]
