DESCRIPTION OF PIN FUNCTIONS
TQFP/STQFP
PIN #
23:20
24
25
26
27
28
29
30
17
BUFFER
TYPE PER
1
SYMBOL
FUNCTION
LPC INTERFACE
LAD[3:0]
PCI_IO
NAME
LPC Address/
Data bus 3-0
LPC Frame
LPC
DMA/Bus Master
Request
PCI RESET
LPC Power Down
(Note 2)
PCI Clock
Controller
PCI Clock
Serial IRQ
Power Mgt. Event
(Note 7)
DESCRIPTION
1
2
3
4
Drive Density 0
Drive Density 1
Motor On 0
Disk Change
Active high LPC signals used for
multiplexed command, address and data
bus.
nLFRAME
PCI_I
Active low signal indicates start of new
cycle and termination of broken cycle.
nLDRQ
PCI_O
Active low signal used for encoded
DMA/Bus Master request for the LPC
interface.
nPCI_RESE
PCI_I
Active low signal used as LPC Interface
T
Reset.
nLPCPD
PCI_I
Active low Power Down signal indicates
that the LPC47N227 should prepare for
power to be shut on the LPC interface.
nCLKRUN
PCI_OD
This signal is used to indicate the PCI
clock status and to request that a stopped
clock be started.
PCI_CLK
PCI_CLK
PCI clock input.
SER_IRQ
PCI_IO
Serial IRQ pin used with the PCI_CLK pin
to transfer LPC47N227 interrupts to the
host.
nIO_PME
(O12/OD12) This active low Power Management Event
signal allows the LPC47N227 to request
wakeup.
FLOPPY DISK INTERFACE
DRVDEN0
(O12/OD12) Indicates the drive and media selected.
Refer to configuration registers CR03,
CR0B, CR1F.
DRVDEN1
(O12/OD12) Indicates the drive and media selected.
Refer to configuration registers CR03,
CR0B, CR1F.
nMTR0
(O12/OD12) These active low output selects motor
drive 0.
nDSKCHG
IS
This input senses that the drive door is
open or that the diskette has possibly been
changed since the last drive selection.
This input is inverted and read via bit 7 of
I/O address 3F7H. The nDSKCHG bit also
depends upon the state of the Force Disk
Change bits in the Force FDD Status
Change configuration register (see
subsection CR17 in the Configuration
section).
5
SMSC [ SMSC CORPORATION ]
