USB 2.0 Hi-Speed 3-Port Hub Controller
Datasheet
Chapter 7 Device Interfaces
The USB2533 provides multiple interfaces for configuration and external memory access. This chapter
details the various device interfaces and their usage.
Note: For information on device configuration, refer to Chapter 6, "Device Configuration," on page 26.
7.1
I2C Master Interface
The I2C master interface implements a subset of the I2C Master Specification (Please refer to the
Philips Semiconductor Standard I2C-Bus Specification for details on I2C bus protocols). The device’s
I2C master interface is designed to attach to a single “dedicated” I2C EEPROM for loading
configuration data and conforms to the Standard-Mode I2C Specification (100 kbit/s transfer rate and
7-bit addressing) for protocol and electrical compatibility. The device acts as the master and generates
the serial clock SCL, controls the bus access (determines which device acts as the transmitter and
which device acts as the receiver), and generates the START and STOP conditions.
Note: Extensions to the I2C Specification are not supported.
Note: All device configuration must be performed via the SMSC Pro-Touch Programming Tool. For
additional information on the Pro-Touch programming tool, contact your local SMSC sales
representative.
2
7.1.1
I C Message Format
7.1.1.1
Sequential Access Writes
The I2C interface supports sequential writing of the device’s register address space. This mode is
useful for configuring contiguous blocks of registers. Figure 7.1 shows the format of the sequential
write operation. Where color is visible in the figure, blue indicates signaling from the I2C master, and
gray indicates signaling from the slave.
S
7-Bit Slave Address
0
A
xxxxxxxx
A
nnnnnnnn
A
...
nnnnnnnn
A
P
Register
Address
(bits 7-0)
Data value for
XXXXXX
Data value for
XXXXXX + y
Figure 7.1 I2C Sequential Access Write Format
In this operation, following the 7-bit slave address, the 8-bit register address is written indicating the
start address for sequential write operation. Every subsequent access is a data write to a data register,
where the register address increments after each access and an ACK from the slave occurs.
Sequential write access is terminated by a Stop condition.
7.1.1.2
Sequential Access Reads
The I2C interface supports direct reading of the device registers. In order to read one or more register
addresses, the starting address must be set by using a write sequence followed by a read. The read
register interface supports auto-increment mode. The master must send a NACK instead of an ACK
when the last byte has been transferred.
SMSC USB2533
31
Revision 1.0 (06-17-13)
DATASHEET
SMSC [ SMSC CORPORATION ]
