Hi-Speed USB Transceiver with 1.8V-3.3V ULPI Interface - 26MHz Reference Clock
Table 1 USB3317 Pin Description (continued)
Output,
CMOS
7
E2
8
E3
9
D3
10
E4
11
D4
12
E5
13
D5
14
C4
15
C5
16
B4
17
B5
CPEN
I/O,
CMOS
I/O,
CMOS
I/O,
CMOS
I/O,
CMOS
Output,
CMOS
I/O,
CMOS
I/O,
CMOS
I/O,
CMOS
I/O,
CMOS
Power
VDDIO
Output,
CMOS
18
A5
High
N/A
High
External 5 volt supply enable. This pin is
used to enable the external Vbus power
supply. The
CPEN
pin is low on POR.
This pad uses VDD3.3 logic level.
ULPI bi-directional data bus.
DATA[7]
is
the MSB.
DATA[7]
N/A
ULPI bi-directional data bus.
N/A
ULPI bi-directional data bus.
N/A
ULPI bi-directional data bus.
N/A
60MHz reference clock output. All ULPI
signals are driven synchronous to the
rising edge of this clock.
DATA[6]
DATA[5
DATA[4]
CLKOUT
N/A
ULPI bi-directional data bus.
N/A
ULPI bi-directional data bus.
N/A
ULPI bi-directional data bus.
N/A
ULPI bi-directional data bus.
DATA[0]
is
the LSB.
1.8V to 3.3V ULPI interface supply
voltage. This voltage sets the value of
V
OH
for the ULPI interface.
The PHY asserts
NXT
to throttle the data.
When the Link is sending data to the
PHY,
NXT
indicates when the current
byte has been accepted by the PHY. The
Link places the next byte on the data bus
in the following clock cycle.
Controls the direction of the data bus.
When the PHY has data to transfer to the
Link, it drives
DIR
high to take ownership
of the bus. When the PHY has no data to
transfer it drives
DIR
low and monitors
the bus for commands from the Link.
The Link asserts
STP
for one clock cycle
to stop the data stream currently on the
bus. If the Link is sending data to the
PHY,
STP
indicates the last byte of data
was on the bus in the previous cycle.
External 1.8V Supply input pin. This pad
needs to be bypassed with a 0.1uF
capacitor to ground, placed as close as
possible to the USB3317.
DATA[3]
DATA[2]
DATA[1]
DATA[0]
N/A
NXT
Output,
CMOS
N/A
19
A4
DIR
Input,
CMOS
High
20
A3
STP
Power
N/A
21
B3
VDD1.8
Revision 1.3 (11-02-07)
6
SMSC USB3317
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