USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
5.1
5.1.1
Boot Sequence
Standby Mode
If the external hardware reset is asserted, the hub will be in Standby Mode. This mode provides a very
low power state for maximum power efficiency when no signaling is required. This is the lowest power
state. In Standby Mode all internal regulators are powered off, the PLL is not running, and core logic
is powered down in order to minimize power consumption. Because core logic is powered off, no
configuration settings are retained in this mode and must be re-initialized after RESET_N is negated
high.
5.1.2
Hardware Initialization Stage (HW_INIT)
The first stage is the initialization stage and occurs on the negation of RESET_N. In this stage the
1.2V regulator is enabled and stabilizes, internal logic is reset, and the PLL locks if a valid REFCLK
is supplied. Configuration registers are initialized to their default state and strap input values are
latched. The device will complete initialization and automatically enter the next stage. Because the
digital logic within the device is not yet stable, no communication with the device using the SMBus is
possible. Configuration registers are initialized to their default state.
If there is no REFCLK present, the next state is BC_INIT. If there is a REFCLK present, the next state
is SW_INIT.
5.1.3
Battery Charging Initialization Stage (BC_INIT)
This state is entered to deal with the dead battery condition. The processor Ring Oscillator (RO) is
enabled. The processor is woken up for a short period. In that period, the processor reads the OTP
to determine what type(s) of upstream battery charging detection will be done. Based on the settings,
the firmware will program the upstream battery charging registers appropriately.
The processor loads the battery charging registers with the values out of OTP memory. Once the
processor has initialized the BC registers, it turns off the ring oscillator. If the hardware detects the
presence of REFCLK, it switches over to regular operation of the PLL.
5.1.4
Wait REFCLK Stage (WAITREF)
In this stage, the reference clock is checked for activity. If the reference clock is active, the device will
continue to the Hub configuration stage. If the reference clock is not active but battery charger
detection is enabled, the detection sequence will begin while operating on an internal ring oscillator.
If the PLL locks while battery charger detection is still in progress, the sequence will be aborted until
the battery charger detection stage. If aborted, no results are captured. If battery charger detection
completes, the results of the battery charger detection may be communicated through the INT_N pin
function, CHRGDET pin function or neither based on the default ROM settings.
If the reference clock is provided before entering hub mode, the device will transition to the Software
Initialization stage (SW_INIT) without pausing in the WAITREF stage. Otherwise, the device will
transition to the SW_INIT stage once a valid reference clock is supplied and the PLL has locked. If
the hardware detects the presence of REFCLK, it switches over to regular operation of the PLL.
Note:
During this stage the SMbus is not functional.
5.1.5
Software Initialization Stage (SW_INIT)
Once the hardware is initialized, the firmware can begin to execute. The internal firmware checks for
an external SPI ROM. The firmware looks for an external SPI flash device that contains a valid
SMSC USB3813
21
Revision 1.0 (06-17-13)
DATASHEET
SMSC [ SMSC CORPORATION ]
