USB 2.0 ATA/ATAPI Controller
Datasheet
Chapter 4
Block Diagram
512 Bytes EP2 TX/RX Buffer B
512 Bytes EP2 TX/RX Buffer A
64 Bytes EP1RX
64 Bytes EP1TX
64 Bytes EP0RX
EP0RX_BC
Address
64 Bytes EP0TX
Auto address generators
1.25KB
SRAM
Address
EP0TX_BC
Address
Data Buss
EP1TX_BC
EP1RX_BC
Address
Address
Address MUX
32 Bit
60MHz
RAMWR_A/B
Address
Latch phase 0
Latch phase 1
Latch phase 2
Future phase 3
Clocked byPhase 2 Clock
RAMRD_A/B
Address
Address Register
Data @ 32 bit
15MHz
XDATA
8 bits ( Address and Data busses )
ATA-66
Interface
ATA/ATAPI
Drive
Clocked byPhase 0 Clock
SIE
( Serial Interface Engine )
32 bit 15MHz Data Buss
SIE Control Regs
USB 2.0 PHY
( Transciever )
Configuration and Control
GPIO
7 pins
Clock Generation
7 pins
Interrupt Controller
Osc
768 Byte
Program/Scratchpad
SRAM
48KB ROM
ROMEN
MEM/IO Bus
OPTIONAL
External PHY
CLOCKOUT
XTAL
29pins
Program Memory/ IO
Bus
FAST 8051
CPU CORE
Debug
Serial 2 wire ( Data/Strobe)
12 MHz
2 pins
Clocked byPhase 1 Clock
SMSC USB97C202
Page 8
Revision 1.6 (01-09-07)
DATASHEET
SMSC [ SMSC CORPORATION ]
