5.0 PIN DESCRIPTIONS
IDE DMA
Request
IDE IO Read
Strobe
IDE Register
Address 1
IDE Register
Address 0
IDE Register
Address 2
IDE Data
IDE_DRQ
DISK DRIVE INTERFACE
IS
This pin is the active high DMA request from
the ATA/ATAPI interface.
O20
This pin is the active low read signal for the
interface.
This pin is the register select address bit 1
signal for the ATA/ATAPI interface.
This pin is the register select address bit 0
signal for the ATA/ATAPI interface.
This pin is the register select address bit 2
signal for the ATA/ATAPI interface.
This pin is the bi-directional data bus bit 15
signal for the ATA/ATAPI interface.
This pin is active low write signal for the
ATA/ATAPI interface.
This pin is the active low DMA acknowledge
signal for the ATA/ATAPI interface.
This pin is the active high interrupt request
signal for the ATA/ATAPI interface.
This pin is the bi-directional data bus bit 13
signal for the ATA/ATAPI interface.
This pin is the bi-directional data bus bit 14
signal for the ATA/ATAPI interface.
.
This pin is the active low chip select 0 signal
for the ATA/ATAPI interface.
This pin is the active low select 1 signal for the
ATA/ATAPI interface.
These pins are bits 0-12 of the ATA/ATAPI bi-
directional data bus.
This pin is the active high IORDY signal from
the IDE drive.
IDE_nIOR
IDE_SA1
O20
IDE_SA0
O20
IDE_SA2
O20
IDE_D15
IO20
IDE IO Write
Strobe
IDE_nIOW
O20
IDE DMA
IDE_nDACK
Acknowledge
IDE Interrupt
Request
IDE Data
IDE_IRQ
O20
IS
IDE_D13
IO20
IDE Data
IDE_D14
IO20
IDE Chip
Select 0
IDE Chip
Select 1 0
IDE Data
IO Ready
IDE_nCS0
O20
IDE_nCS1
O20
IDE_D[0:12]
IORDY
IO20
I
SMSC DS – USB97C201
Page 10
Rev. 03/25/2002
PRELIMINARY
SMSC [ SMSC CORPORATION ]
