CXA1782CQ/CR
Block Diagram
RF_M
PHD2
PHD1
PHD
RF_O
RF_I
CP
36
35
34
33
32
31
30
29
28
CB
27
26
25
APC
LEVEL S
I IL
24 SENS
FOK
CC1
CC2
LD
TTL
23 C.OUT
RF IV AMP1
MIRR
FOK
DFCT
22 XRST
TTL
RF IV AMP2
FE_BIAS 37
TTL
•I IL DATA REGISTER •INPUT SHIFT REGISTER
•ADRESS.DECODER
21 DATA
I IL
20 XLT
F 38
FE AMP
F IV AMP
I IL
•OUTPUT DECODER
19 CLK
E 39
FZC COMP
E IV AMP
EI 40
TE AMP
TOG1 to 3 FS1 to 4 TG1 to 2 TM1 to 7
BAL1 to 3
PS1 to 4
18 Vcc
BAL2
BAL1
BAL3
HPF COMP LPF COMP
•TRACKING
PHASE COMPENSATION
TM6
•I SET
17 ISET
V
EE
41
TEO 42
TG1
16 SL_O
TM5
TOG2
TOG1
TOG3
TM4
TZC COMP
DFCT
TM1
•FCS PHASE COMPENSATION
FS1
TM7
TM3
TM2
15 SL_M
LPFI 43
14 SL_P
TEI 44
ATSC 45
TZC 46
TDFCT 47
DFCT
VC 48
FS4
•WINDOW COMP.
ATSC
FS2
TG2
13 TA_O
1
2
3
4
5
6
7
8
9
10
11
•F SET
12
FE_M
FDFCT
SRCH
FE_O
TGU
FSET
FLB
FEI
•
The switch state in Block Diagram is for initial resetting.
•
Switch turns to ° side for 1 and to
•
side for 0 in Serial Data Truth Table.
•
DFCT switch turns to ° side when defect signal generates for DEFECT = E in Serial Data Truth Table.
•
TG1 switch turns to ° side and TG2 switch is left open when TG1 and TG2 (address 1 : D3) is 1.
–2–
TA_M
FEO
FGD
TG2
SONY [ SONY CORPORATION ]
