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CXD1852Q 参数 Datasheet PDF下载

CXD1852Q图片预览
型号: CXD1852Q
PDF下载: 下载PDF文件 查看货源
内容描述: MPEG1解码器 [MPEG1 Decoder]
分类和应用: 解码器消费电路商用集成电路
文件页数/大小: 30 页 / 380 K
品牌: SONY [ SONY CORPORATION ]
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CXD1852Q
MPEG1 Decoder
For the availability of this product, please contact the sales office.
Description
The CXD1852Q is a single-chip MPEG1 decoder
with a built-in CD-ROM decoder which allows
decoding of MPEG1 system, video and audio layers.
A built-in CD-ROM decoder enables direct connection
with a CD-DSP. Combining this chip with a control
microcomputer and 4-Mbit DRAM, etc. allows
configuration of a MPEG1 decoding system for video
CD players, etc.
Features
Supply voltage: 3.3 ± 0.3V
Input and output voltages: LVTTL compatible
5V can be applied as the input voltage (excluding
some pins)
Allows decoding of MPEG1 system, video and
audio layers
Built-in CD-ROM decoder allows direct connection
with a CD-DSP
CD-ROM decoded output can be transferred to
and stored in an external DRAM
RGB and YCbCr video data output allowed
Built-in video sync generator
Audio data output can support various DAC
Supports various special playback modes
Video CD PAL high resolution still picture can be
decoded with a single 4-Mbit DRAM
8-bit parallel and 4-line serial host interfaces
CD-DA through operation allowed
Block Diagram
120 pin QFP (Plastic)
Structure
Silicon gate CMOS IC
Applications
Video CD players, MPEG1 decoder boards, etc.
CD-DSP
I/F
CD-ROM
Decoder
MPEG
System
Decoder
MPEG
Audio
Decoder
Audio
I/F
To each circuit block
MPEG
Video
Decoder
Host
interface
DRAM
Controler
Video Postprocessor
&
Sync Generator
Video
I/F
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
Video Sync
Signal
DRAM
I/F
Host
I/F
E96656-PS