CXD1968AR
COFDM Demodulator Core
The main processing functions are;
10-bit ADC
IF Input Mode
Input to the CXD1968AR is a differential IF signal centered at either 4.57MHz or nominally 36.167MHz.
The exact IF frequency can be set via the ITB_FREQ_1 and ITB_FREQ_2 registers. An integrated
10-bit A/D converter clocked at 20.48MHz is used to sample the IF signal. Input amplitude is nominally
1V peak-to-peak differential, but can also be set to 0.7V, 1.5V, or 2V peak-to-peak differential using I
2
C
registers.
Zero IF (ZIF) Input Mode
The I channel uses the same ADC described above for IF input signals. A second 10-bit ADC is used
for the Q channel input. Both ADCs sample at 20.48MHz. Input amplitude is nominally 1V peak-to-peak
differential, but can also be set to 0.7V, 1.5V, or 2V peak-to-peak differential using I
2
C registers.
Power Estimation (AGC)
IF Mode
This block monitors the signal level at the output of the ADC and provides a Pulse Width Modulated
(PWM) control signal to drive an external (analog) variable gain amplifier (VGA) in the tuner IF stage.
This circuit operates as an automatic gain control loop and is normally configured to maximize ADC
dynamic range determined by a fixed AGC target value. The enhanced AGC system modifies the AGC
gain according to the characteristics of the received channel in order to better cope with interferers. The
AGC output voltage is generated as a PWM signal and requires a simple external single pole RC filter
to interface with the AGC system. The AGC gain value applied to the external amplifier can be read via
a register to assist software RF AGC algorithms.
Zero IF (ZIF) Input Mode
In ZIF input mode, both the I and Q channels are monitored independently, each driving a separate
PWM control signal (IFAGC_I, RF_IFAGC_Q) to allow separate tuner AGC amplifiers to correct for I/Q
amplitude imbalances. Other features are similar to IF-mode AGC described above.
Automatic Gain Control – External RF
This block provides an additional Pulse Width Modulated (PWM) control signal (RF_IFAGC_Q) to drive the
variable gain amplifier (VGA) in the tuner RF stage. The output value is set by an I
2
C register. This feature
is only available in IF input mode. In ZIF mode this pin is used by the Q channel AGC PWM output.
General-purpose I/O Port
The RF AGC pin can be configured to generate a logic level signal in place of the PWM output. This may
be used for SAW switching, test output or other user-defined purpose. Alternatively this pin can be
programed as a digital input, readable by I
2
C. The above features are only available in IF input mode. In
ZIF mode this pin is used by the Q channel AGC PWM output.
IF to Baseband Conversion (ITB)
This block translates the received digitized IF signal to complex baseband. Subsequent processing is
performed on the complex baseband samples. This block is not used in ZIF input mode.
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SONY [ SONY CORPORATION ]
