CXD2510Q
2. CLOK, DATA, XLAT, CNIN, SQCK EXCK pins
(V
DD
= AV
DD
= 5.0V ± 10%, V
SS
= AV
SS
= 0V, Topr = –20 to +75°C)
Item
Clock frequency
Clock pulse width
Setup time
Hold time
Delay time
Latch pulse width
EXCK SQCK frequency
Symbol
f
CK
Min.
Typ.
Max.
0.65
750
300
300
300
750
0.65
750
65
7.5
Unit
MHz
ns
ns
ns
ns
ns
MHz
ns
kHz
µs
t
WCK
t
SU
t
H
t
D
t
WL
f
T
EXCK SQCK pulse width
t
WT
CNIN freqency
∗
f
T
CNIN pulse width
∗
t
WT
∗
When $44 and $45 are excuted.
1/f
CK
t
WCK
CLOK
t
WCK
DATA
XLAT
EXCK
CNIN
SQCK
t
SU
t
H
t
D
t
WL
t
WT
1/f
T
t
WT
SBSO
SQSO
t
SU
t
H
Description of Functions
§1. CPU Interface and Instructions
•
CPU interface
This interface uses DATA, CLOK, and XLAT to set the modes.
The interface timing chart is shown below.
750ns or more
CLOK
DATA
D1
D2
D3
D0
D1
D2
D3
750ns or more
Data
XLAT
Address
Registers 4 to E
Valid
300ns max
• Information on each address and the data is provided in Table 1-1.
• The internal registers are initialized by a reset when XRST = 0; the initialization data is shown in Table 1-2.
–8–
SONY [ SONY CORPORATION ]
