CXD3009Q
Pin
No.
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
Symbol
BIAS
ASYI
ASYO
LRCK
LRCKI
PCMD
PCMDI
BCK
BCKI
V
SS
V
DD
XUGF
XPCK
GFS
C2PO
XTSL
C4M
DOUT
EMPH
EMPHI
WFCK
SCOR
SBSO
EXCK
V
SS
V
DD
SYSM
AV
SS
AV
DD
AOUT1
AIN1
LOUT1
AV
SS
XV
DD
XTAI
XTAO
I
O
I
I
O
O
I
O
I
O
I
—
—
O
O
O
O
I
O
O
O
I
O
O
O
I
—
—
I
—
—
O
I
O
—
I/O
Description
Constant current input of the asymmetry circuit.
Asymmetry comparator voltage input.
1, 0
1, 0
EFM full-swing output (low = V
SS
, high = V
DD
).
D/A interface. LR clock output f = Fs.
LR clock input.
1, 0
D/A interface. Serial data output (two's complement, MSB first).
D/A interface. Serial data input (two's complement, MSB first).
1, 0
D/A interface. Bit clock output.
D/A interface. Bit clock input.
—
—
1, 0
1, 0
1, 0
1, 0
GND
Power supply (+3V).
XUGF output. Switched to MNT1 or RFCK output by a command.
XPLCK output. Switched to MNT0 output by a command.
GFS output. Switched to MNT3 or XRAOF output by a command.
C2PO output. Switched to GTOP output by a command.
Crystal selector input. Low: 16.9344MHz; high: 33.8688MHz.
1, 0
1, 0
1, 0
4.2336MHz output. 1/4 frequency-divided VCKI output in CAV-W mode.
Digital Out output.
Outputs a high signal when the playback disc has emphasis, and a low
signal when there is no emphasis.
Inputs a high signal when de-emphasis is on, and a low signal when
de-emphasis is off.
1, 0
1, 0
1, 0
WFCK output.
Outputs a high signal when either subcode sync S0 or S1 is detected.
Sub P to W serial output.
SBSO readout clock input.
—
—
GND
Power supply (+3V).
Mute input. Active when high.
—
—
Analog GND.
Analog power supply (+3V).
Left-channel analog output.
Left-channel operational amplifier input.
Left-channel LINE output.
—
Analog GND.
Power supply for master clock.
Crystal oscillation circuit input. Input the external master clock via this pin.
Crystal oscillation circuit output.
–5–
SONY [ SONY CORPORATION ]
