CXL1503M/1505M
Block Diagram
XDL1
XDL2
V
DD
V
DD
V
SS
V
DD
V
SS
19
ABCN 21
A. B
CENTER
TIMING GENERATOR
ABBL 3
DCAB 23
5V
IN A 22
CLP
DL A
A. B
BLACK
P. D
P. D
PG GEN.
CDS-OUTPUT
CIRCUIT
PG GEN.
IN B 24
CLP
DL B
PG GEN.
IN C 2
CLP
DL C
CDS-OUTPUT
CIRCUIT
PG GEN.
IN D 6
CLP
DL D
CDS-OUTPUT
CIRCUIT
9
OUT D
11 OUT C
CDS-OUTPUT
CIRCUIT
13 OUT B
15 OUT A
18
4
8
1
16
20
17
Pin Configuration
(Top View)
V
SS
V
SS
1
IN C 2
ABBL 3
V
DD
4
IS 5
IN D 6
CLP 7
V
DD
8
OUT D 9
V
GG
10
OUT C 11
N.C. 12
24 IN B
23 DCAB
22 IN A
21 ABCN
20 V
DD
19 XDL1
18 XDL2
17 V
SS
16 V
SS
15 OUT A
14 CDS
13 OUT B
WAVE
FORM
7
5
INPUT
SOURCE
12
POTENTIAL
CONTROL
10
14
BIAS.
Pin Description
No.
Symbol
I/O
—
I
O
—
O
I
I
O
O
O
—
O
O
O
I
I
O
I
I
I
Signal output B channel
DC output for CDS
Signal output A channel
Clock pulse input 2
Clock pulse input 1
Autobias DC output for C signal
Signal input A channel
DC bias input for A and B channel
Signal input B channel
–2–
GND
Signal input C channel
Autobias DC output for Y signal
5V power supply
Input source DC output
Signal input D channel
Clamp pulse input
Signal output D channel
Gate bias DC output
Signal output C channel
—
50 to 500
500 to 5k
50 to 500
> 100k
> 100k
2k to 20k
> 100k (at no clamp)
> 100k
> 100k (at no clamp)
5k
> 100k (at no clamp)
> 100k
50 to 500
2k to 10k
50 to 500
> 100k (at no clamp)
2k to 20k
Description
Impedance (Ω)
1, 16, 17 V
SS
2
3
4, 8, 20
5
6
7
9
10
11
12
13
14
15
18
19
21
22
23
24
IN C
ABBL
V
DD
IS
IN D
CLP
OUT D
V
GG
OUT C
N.C.
OUT B
CDS
OUT A
XDL2
XDL1
ABCN
IN A
DCAB
IN B
CDS
CLP
N.C.
V
GG
IS
SONY [ SONY CORPORATION ]
