CXL5001M/P
CMOS-CCD 1H Delay Line for NTSC
Description
The CXL5001M/P are general-purpose CMOS-CCD
delay line ICs that provide 1H delay time for NTSC.
Features
•
Low power consumtion 80mW (Typ.)
•
Small size package (8-pin SOP, DIP)
•
Low differential gain DG = 3% (Typ.)
•
Input signal ampiitude 180 IRE (= 1.28Vp-p, Max.)
•
Low input clock amplitude operation 150mVp-p (Min.)
•
Built-in peripheral circuits (clock driver, timing
generator, autobias, and output circuits)
Functions
•
680-bit CCD register
•
Clock drivers
•
Autobias circuit
•
Sync tip clamp circuit
•
Sample and hold circuit
Structure
CMOS-CCD
Absolute Maximum Ratings
(Ta = 25°C)
•
Supply voltage
V
DD
11
•
Supply voltage
V
CL
6
CXL5001M
8 pin SOP (Plastic)
CXL5001P
8 pin DIP (Plastic)
V
V
•
Operating temperature
Topr –10 to +60 °C
•
Storage temperature
Tstg –55 to +150 °C
•
Allowable power dissipation P
D
CXL5001M 350 mW
CXL5001P 480 mW
Recommended Operating Conditions
Supply voltage
V
DD
9 ± 5%
V
V
CL
5 ± 5%
V
Recommended Clock Conditions
•
Input clock amplitude
V
CLK
150mVp-p to 1.0Vp-p
(250mVp-p typ.)
•
Clock frequency
f
CLK
10.7MHz
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E50799A78-PS
SONY [ SONY CORPORATION ]
