CXL5509M/P
CMOS-CCD 1H/2H Delay Line for NTSC
Description
The CXL5509M/P is a CMOS-CCD delay line
developed for video signal processing. Usage in
conjunction with an external low-pass filter provide 1H
and 2H delay signals simultaneously (For NTSC
signals).
Features
•
Single power supply (5V)
•
Low power consumption 130mW (Typ.)
•
Built-in peripheral circuits
•
Built-in quadruple PLL circuit
•
For NTSC signals
•
1 input and 2 outputs
(Outputs for both 1H and 2H delays)
Functions
•
906-bit (1H) and 1816-bit (2H) CCD register
•
Clock driver
•
Auto-bias circuit
•
Sync tip clamp circuit
•
Sample-and-hold circuit
•
Quadruple PLL circuit
Structure
CMOS-CCD
CXL5509M
16 pin SOP (Plastic)
CXL5509P
16 pin DIP (Plastic)
Absolute Maximum Ratings
(Ta = 25°C)
6
V
•
Supply voltage
V
DD
•
Operating temperature Topr
–10 to +60
°C
•
Storage temperature Tstg
–55 to +150 °C
•
Allowable power dissipation
P
D
CXL5509M
400
mW
CXL5509P
800
mW
Recommended Operating Condition
(Ta = 25°C)
Supply voltage
V
DD
5 ± 5%
V
Recommended Clock Conditions
(Ta = 25°C)
•
Input clock amplitude V
CLK
0.3 to 1.0
Vp-p
(0.5Vp-p typ.)
•
Clock frequency
f
CLK
3.579545
MHz
•
Input clock waveform sine wave
Input Signal Amplitude
V
SIG
571mVp-p (Max.) (at internal clamp condition)
PC OUT
Blook Diagram and Pin Configuration
(Top View)
VCO IN
V
DD
V
SS
AB
CLK
16
15
14
13
V
SS
12
11
10
Auto-bias circuit
PLL
Driver
Timing circuit
Clamp circuit
CCD
(1816bit)
906bit
Output circuit
(S/H 1bit)
1816bit
Output circuit
(S/H 1bit)
Bias circuit
1
2
3
4
5
6
7
IN
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
V
SS
(VCO OUT)
VG1
VG2
OUT1 (1H)
V
SS
OUT2 (2H)
V
SS
V
DD
9
8
E91401B7X-PS
SONY [ SONY CORPORATION ]
