CXP83408/83412/83416, CXP83409/83413/83417
I/O Circuit Format for Pins
Pin
Port A
Pull-up resistor
“0” when reset
Port A data
Circuit format
∗
When reset
PA0/AN0
to
PA7/AN7
Data bus
Port A direction
“0” when reset
IP Input protection
circuit
Hi-Z
RD (Port A)
Port A input selection
“0” when reset
Input multiplexer
A/D converter
8 pins
Port B
Pull-up resistor
“0” when reset
Port B data
∗
Pull-up resistors
approx. 100kΩ
∗
PB0/CS1
PB1/CS0
PB3/SI0
PB6/SI1
Data bus
Port B direction
“0” when reset
IP
Schmitt input
Hi-Z
RD (Port B)
CS1
CS0
SI0
SI1
4 pins
Port B
Pull-up resistor
“0” when reset
SCK OUT
Output enable
Port B output
selection
“0” when reset
Port B data
Port B direction
“0” when reset
Data bus
RD (Port B)
∗
Pull-up transistors
approx. 100kΩ
∗
PB2/SCK0
PB5/SCK1
Hi-Z
IP
Schmitt input
2 pins
SCK in
∗
Pull-up transistors
approx. 100kΩ
–8–
SONY [ SONY CORPORATION ]
