ICX255AK
Block Diagram and
Pin Configuration
(Top View)
V
OUT
GND
Vφ
1
Vφ
3
2
Ye
G
Ye
Mg
Ye
G
8
7
6
5
Vφ
2
4
3
Cy
Ye
G
Ye
Mg
Ye
G
Cy
Mg
Cy
G
Cy
Mg
Vertical Register
Mg
Cy
G
Cy
Mg
Horizontal Register
Note)
: Photo sensor
9
10
11
12
13
14
15
16
GND
φSUB
φRG
Hφ
1
V
DD
Pin Description
Pin No.
1
2
3
4
5
6
7
8
Symbol
Vφ
4
Vφ
3
Vφ
2
Vφ
1
GND
NC
NC
V
OUT
Signal output
Description
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
GND
Pin No.
9
10
11
12
13
14
15
16
Hφ
2
V
L
NC
Vφ
4
1
Note)
NC
NC
Symbol
V
DD
GND
φSUB
V
L
φRG
NC
Hφ
1
Hφ
2
Description
Supply voltage
GND
Substrate clock
Protective transistor bias
Reset gate clock
Horizontal register transfer clock
Horizontal register transfer clock
Absolute Maximum Ratings
Item
V
DD
, V
OUT
,
φRG
–
φSUB
Against
φSUB
Vφ
1
, Vφ
3
–
φSUB
Vφ
2
, Vφ
4
, V
L
–
φSUB
Hφ
1
, Hφ
2
, GND –
φSUB
V
DD
, V
OUT
,
φRG
– GND
Against GND
Vφ
1
, Vφ
2
, Vφ
3
, Vφ
4
– GND
Hφ
1
, Hφ
2
– GND
Against V
L
Vφ
1
, Vφ
3
– V
L
Vφ
2
, Vφ
4
, Hφ
1
, Hφ
2
, GND – V
L
Voltage difference between vertical clock input pins
Between input clock
pins
Storage temperature
Operating temperature
∗
1
+24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
–2–
Hφ
1
– Hφ
2
Hφ
1
, Hφ
2
– Vφ
4
Ratings
–40 to +8
–50 to +15
–50 to +0.3
–40 to +0.3
–0.3 to +20
–10 to +18
–10 to +6
–0.3 to +28
–0.3 to +15
to +15
–6 to +6
–14 to +14
–30 to +80
–10 to +60
Unit
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
∗
1
Remarks
SONY [ SONY CORPORATION ]
