ICX408AL
Clock Switching Characteristics
Item
Readout clock
Vertical transfer
clock
Horizontal
transfer clock
During
imaging
Symbol
V
T
Vφ
1
, Vφ
2
,
Vφ
3
, Vφ
4
Hφ
1
Hφ
2
26 28.5
26 28.5
5.38
5.38
11
13
51
26 28.5
26 28.5
6.5 9.5
6.5 9.5
0.01
0.01
3
0.5
twh
twl
tr
tf
Unit Remarks
µs
During
readout
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
2.3 2.5
0.5
15
0.5
250 ns
∗
1
6.5 9.5
6.5 9.5
0.01
0.01
3
0.5
ns
µs
During drain
charge
µs
ns
∗
2
During
Hφ
1
parallel-serial
Hφ
2
conversion
φRG
φSUB
Reset gate clock
Substrate clock
1.5 1.8
∗
1
When vertical transfer clock driver CXD1267AN is used.
∗
2
tf
≥
tr – 2ns, and the cross-point voltage (V
CR
) for the Hφ
1
rising side of the Hφ
1
and Hφ
2
waveforms must be
at least Vφ
H
/2 [V].
Item
Horizontal transfer clock
Symbol
Hφ
1
, Hφ
2
two
Min.
22
Typ.
26
Max.
Unit
ns
Remarks
∗
3
∗
3
The overlap period for twh and twl of horizontal transfer clocks Hφ
1
and Hφ
2
is two.
–7–
SONY [ SONY CORPORATION ]
