ICX412AQF
Bias Conditions
Item
Supply voltage
Protective transistor bias
Substrate clock
Reset gate clock
Symbol
V
DD
V
L
φSUB
φRG
Min.
14.55
Typ.
15.0
∗
1
∗
2
∗
2
Max.
15.45
Unit
V
Remarks
∗
1
V
L
setting is the V
VL
voltage of the vertical clock waveform, or the same voltage as the V
L
power supply for
the V driver should be used.
∗
2
Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated
within the CCD.
DC Characteristics
Item
Supply current
Symbol
I
DD
Min.
5.5
Typ.
7.5
Max.
9.5
Unit
mA
Remarks
Clock Voltage Conditions
Item
Readout clock voltage
Symbol
V
VT
V
VH1
, V
VH2
V
VH3
, V
VH4
V
VL1
, V
VL2
,
V
VL3
, V
VL4
Vφ
V
Vertical transfer clock
voltage
V
VH3
– V
VH
V
VH4
– V
VH
V
VHH
V
VHL
V
VLH
V
VLL
Vφ
H
Horizontal transfer
clock voltage
V
HL
V
CR
Vφ
RG
Reset gate clock
voltage
V
RGLH
– V
RGLL
V
RGL
– V
RGLm
Substrate clock voltage Vφ
SUB
21.5
22.5
4.0
–0.05
0.8
3.0
5.0
0
2.5
3.3
5.25
0.4
0.5
23.5
Min.
14.55
–0.05
–0.2
–8.0
6.8
–0.25
–0.25
Typ.
15.0
0
0
–7.5
7.5
Max. Unit
15.45
0.05
0.05
–7.0
8.05
0.1
0.1
0.8
0.9
0.9
0.8
5.25
0.05
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Waveform
Diagram
1
2
2
2
2
2
2
2
2
2
2
3
3
3
4
4
4
5
Low-level coupling
Low-level coupling
Cross-point voltage
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
V
VL
= (V
VL3
+ V
VL4
)/2
Vφ
V
= V
VH
n – V
VL
n (n = 1 to 4)
V
VH
= (V
VH1
+ V
VH2
)/2
Remarks
–4–
SONY [ SONY CORPORATION ]
