D A T A S H E E T
Table 3. Am29F010B Autoselect Codes (High Voltage Method)
A16 A13
to to
CE# OE# WE# A14 A10 A9
A8
to
A7
A5
to
A2
DQ7
to
DQ0
Description
Manufacturer ID: AMD
Device ID: Am29F010B
A6
L
A1
L
A0
L
L
L
L
L
H
H
X
X
X
X
VID
VID
X
X
X
X
01h
20h
L
L
H
01h
(protected)
Sector Protection Verification
L
L
H
SA
X
VID
X
L
X
H
L
00h
(unprotected)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
gramming, which might otherwise be caused by
Sector Protection/Unprotection
spurious system level signals during V power-up and
CC
The hardware sector protection feature disables both
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors.
power-down transitions, or from system noise.
Low V
Write Inhibit
CC
When V
is less than V
, the device does not ac-
LKO
CC
cept any write cycles. This protects data during V
CC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
Sector protection/unprotection must be implemented
using programming equipment. The procedure re-
device resets. Subsequent writes are ignored until V
quires a high voltage (V ) on address pin A9 and the
CC
ID
is greater than V
. The system must provide the
control pins. Details on this method are provided in a
supplement, publication number 22337. Contact an
AMD representative to obtain a copy of the appropriate
document.
LKO
proper signals to the control pins to prevent uninten-
tional writes when V is greater than V
.
CC
LKO
Write Pulse “Glitch” Protection
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V , CE# = V or WE# = V . To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
IL
IH
IH
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Hardware Data Protection
Power-Up Write Inhibit
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
If WE# = CE# = V and OE# = V during power up, the
IL IH
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
October 31, 2006 Am29F010B_00_C7
Am29F010B
9
SPANSION [ SPANSION ]
