DATA SHEET
GENERAL DESCRIPTION
The Am29F160D is a 16 Mbit, 5.0 Volt-only Flash
memory device organized as 2,097,152 bytes or
1,048,576 words. Data appears on DQ0-DQ7 or DQ0-
DQ15 depending on the data width selected. The
device is designed to be programmed in-system with
the standard system 5.0 volt V
CC
supply. A 12.0 volt
V
PP
is not required for program or erase operations.
The device can also be programmed in standard
EPROM programmers.
The device offers access times of 70 and 90 ns, allowing
high speed microprocessors to operate without wait
states. The device is offered in a 48-pin TSOP
package. To eliminate bus contention each device has
separate chip enable (CE#), write enable (WE#) and
output enable (OE#) controls.
Each device requires only a
single 5.0 volt power
supply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard.
Com-
mands are written to the command register using stan-
dard microprocessor write timing. Register contents
serve as inputs to an internal state-machine that con-
trols the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The
Unlock Bypass mode
facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase
command sequence. This initiates the
Embedded
Erase algorithm—an
internal algorithm that automati-
cally preprograms the array (if it is not already pro-
grammed) before executing the erase operation.
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, by reading the DQ7 (Data# Polling), or DQ6
(toggle)
status bits.
After a program or erase cycle is
completed, the device is ready to read array data or
accept another command.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
VCC detector that automatically inhibits write operations
during power transitions. The
hardware sector protec-
tion
feature disables both program and erase operations
in any combination of sectors of memory. This can be
achieved in-system or via programming equipment.
The
Write Protect (WP#)
feature protects the 16
Kbyte boot sector from erasure, by asserting a logic
low on the WP# pin, whether or not the sector had
been previously protected.
The
Erase Suspend/Erase Resume
feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read boot-up firmware from the Flash memory device.
The device offers a
standby mode
as a power-saving
feature. Once the system places the device into the
standby mode power consumption is greatly reduced.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunnelling.
The data is programmed using hot electron injection.
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Am29F160D
Am29F160D_00_D6 November 2, 2006
SPANSION [ SPANSION ]
