D a t a
S h e e t
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing
provides data protection against inadvertent writes (refer to
Table 5, on page 25
for command definitions). In addition, the following hardware data protection
measures prevent accidental erasure or programming, which might otherwise be
caused by spurious system level signals during V
CC
power-up and power-down
transitions, or from system noise.
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not accept any write cycles. This pro-
tects data during V
CC
power-up and power-down. The command register and all
internal program/erase circuits are disabled, and the device resets. Subsequent
writes are ignored until V
CC
is greater than V
LKO
. The system must provide the
proper signals to the control pins to prevent unintentional writes when V
CC
is
greater than V
LKO
.
Write Pulse
Glitch
Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write
cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V
IL
, CE# = V
IH
or WE# =
V
IH
. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
IL
and OE# = V
IH
during power up, the device does not accept
commands on the rising edge of WE#. The internal state machine is automatically
reset to reading array data on power-up.
Command Definitions
Writing specific address and data commands or sequences into the command
register initiates device operations.
Table 5, on page 25
defines the valid register
command sequences. Writing
incorrect address and data values
or writing
them in the
improper sequence
resets the device to reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens
later. All data is latched on the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
AC Characteristics, on
page 38.
Reading Array Data
The device is automatically set to reading array data after device power-up. No
commands are required to retrieve data. The device is also ready to read array
data after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the Erase
Suspend mode. The system can read array data using the standard read timings,
except that if it reads at an address within erase-suspended sectors, the device
outputs status data. After completing a programming operation in the Erase Sus-
pend mode, the system may once again read array data with the same exception.
See
Erase Suspend/Erase Resume Commands, on page 23
for more information
on this mode.
June 16, 2005 S29AL008D_00A3
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