D a t a
S h e e t
AC Characteristics
t
RC
Addresses
t
POLL
CE#
t
CH
OE#
t
OEH
WE#
t
OH
DQ7
Complement
Complement
True
Valid Data
High Z
VA
t
ACC
t
CE
VA
VA
t
OE
t
DF
DQ0–DQ6
t
BUSY
RY/BY#
Status Data
Status Data
True
Valid Data
High Z
Note:
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array
data read cycle.
Figure 17. Data# Polling Timings
(During Embedded Algorithms)
t
RC
Addresses
VA
t
ACC
t
CE
CE#
t
CH
OE#
t
OEH
WE#
t
OH
DQ6/DQ2
t
BUSY
RY/BY#
Note:
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last
status read cycle, and array data read cycle.
High Z
VA
VA
VA
t
OE
t
DF
Valid Status
(first read)
Valid Status
(second read)
Valid Status
(stops toggling)
Valid Data
Figure 18. Toggle Bit Timings
(During Embedded Algorithms)
48
S29AL016M
S29AL016M_00_A7 October 11, 2006
SPANSION [ SPANSION ]
